1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s 2 3 define <2 x i32> @fcvtas_2s(<2 x float> %A) nounwind { 4 ;CHECK-LABEL: fcvtas_2s: 5 ;CHECK-NOT: ld1 6 ;CHECK: fcvtas.2s v0, v0 7 ;CHECK-NEXT: ret 8 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float> %A) 9 ret <2 x i32> %tmp3 10 } 11 12 define <4 x i32> @fcvtas_4s(<4 x float> %A) nounwind { 13 ;CHECK-LABEL: fcvtas_4s: 14 ;CHECK-NOT: ld1 15 ;CHECK: fcvtas.4s v0, v0 16 ;CHECK-NEXT: ret 17 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float> %A) 18 ret <4 x i32> %tmp3 19 } 20 21 define <2 x i64> @fcvtas_2d(<2 x double> %A) nounwind { 22 ;CHECK-LABEL: fcvtas_2d: 23 ;CHECK-NOT: ld1 24 ;CHECK: fcvtas.2d v0, v0 25 ;CHECK-NEXT: ret 26 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double> %A) 27 ret <2 x i64> %tmp3 28 } 29 30 declare <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float>) nounwind readnone 31 declare <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float>) nounwind readnone 32 declare <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double>) nounwind readnone 33 34 define <2 x i32> @fcvtau_2s(<2 x float> %A) nounwind { 35 ;CHECK-LABEL: fcvtau_2s: 36 ;CHECK-NOT: ld1 37 ;CHECK: fcvtau.2s v0, v0 38 ;CHECK-NEXT: ret 39 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float> %A) 40 ret <2 x i32> %tmp3 41 } 42 43 define <4 x i32> @fcvtau_4s(<4 x float> %A) nounwind { 44 ;CHECK-LABEL: fcvtau_4s: 45 ;CHECK-NOT: ld1 46 ;CHECK: fcvtau.4s v0, v0 47 ;CHECK-NEXT: ret 48 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float> %A) 49 ret <4 x i32> %tmp3 50 } 51 52 define <2 x i64> @fcvtau_2d(<2 x double> %A) nounwind { 53 ;CHECK-LABEL: fcvtau_2d: 54 ;CHECK-NOT: ld1 55 ;CHECK: fcvtau.2d v0, v0 56 ;CHECK-NEXT: ret 57 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double> %A) 58 ret <2 x i64> %tmp3 59 } 60 61 declare <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float>) nounwind readnone 62 declare <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float>) nounwind readnone 63 declare <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double>) nounwind readnone 64 65 define <2 x i32> @fcvtms_2s(<2 x float> %A) nounwind { 66 ;CHECK-LABEL: fcvtms_2s: 67 ;CHECK-NOT: ld1 68 ;CHECK: fcvtms.2s v0, v0 69 ;CHECK-NEXT: ret 70 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float> %A) 71 ret <2 x i32> %tmp3 72 } 73 74 define <4 x i32> @fcvtms_4s(<4 x float> %A) nounwind { 75 ;CHECK-LABEL: fcvtms_4s: 76 ;CHECK-NOT: ld1 77 ;CHECK: fcvtms.4s v0, v0 78 ;CHECK-NEXT: ret 79 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float> %A) 80 ret <4 x i32> %tmp3 81 } 82 83 define <2 x i64> @fcvtms_2d(<2 x double> %A) nounwind { 84 ;CHECK-LABEL: fcvtms_2d: 85 ;CHECK-NOT: ld1 86 ;CHECK: fcvtms.2d v0, v0 87 ;CHECK-NEXT: ret 88 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double> %A) 89 ret <2 x i64> %tmp3 90 } 91 92 declare <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float>) nounwind readnone 93 declare <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float>) nounwind readnone 94 declare <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double>) nounwind readnone 95 96 define <2 x i32> @fcvtmu_2s(<2 x float> %A) nounwind { 97 ;CHECK-LABEL: fcvtmu_2s: 98 ;CHECK-NOT: ld1 99 ;CHECK: fcvtmu.2s v0, v0 100 ;CHECK-NEXT: ret 101 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float> %A) 102 ret <2 x i32> %tmp3 103 } 104 105 define <4 x i32> @fcvtmu_4s(<4 x float> %A) nounwind { 106 ;CHECK-LABEL: fcvtmu_4s: 107 ;CHECK-NOT: ld1 108 ;CHECK: fcvtmu.4s v0, v0 109 ;CHECK-NEXT: ret 110 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float> %A) 111 ret <4 x i32> %tmp3 112 } 113 114 define <2 x i64> @fcvtmu_2d(<2 x double> %A) nounwind { 115 ;CHECK-LABEL: fcvtmu_2d: 116 ;CHECK-NOT: ld1 117 ;CHECK: fcvtmu.2d v0, v0 118 ;CHECK-NEXT: ret 119 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double> %A) 120 ret <2 x i64> %tmp3 121 } 122 123 declare <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float>) nounwind readnone 124 declare <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float>) nounwind readnone 125 declare <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double>) nounwind readnone 126 127 define <2 x i32> @fcvtps_2s(<2 x float> %A) nounwind { 128 ;CHECK-LABEL: fcvtps_2s: 129 ;CHECK-NOT: ld1 130 ;CHECK: fcvtps.2s v0, v0 131 ;CHECK-NEXT: ret 132 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float> %A) 133 ret <2 x i32> %tmp3 134 } 135 136 define <4 x i32> @fcvtps_4s(<4 x float> %A) nounwind { 137 ;CHECK-LABEL: fcvtps_4s: 138 ;CHECK-NOT: ld1 139 ;CHECK: fcvtps.4s v0, v0 140 ;CHECK-NEXT: ret 141 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float> %A) 142 ret <4 x i32> %tmp3 143 } 144 145 define <2 x i64> @fcvtps_2d(<2 x double> %A) nounwind { 146 ;CHECK-LABEL: fcvtps_2d: 147 ;CHECK-NOT: ld1 148 ;CHECK: fcvtps.2d v0, v0 149 ;CHECK-NEXT: ret 150 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double> %A) 151 ret <2 x i64> %tmp3 152 } 153 154 declare <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float>) nounwind readnone 155 declare <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float>) nounwind readnone 156 declare <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double>) nounwind readnone 157 158 define <2 x i32> @fcvtpu_2s(<2 x float> %A) nounwind { 159 ;CHECK-LABEL: fcvtpu_2s: 160 ;CHECK-NOT: ld1 161 ;CHECK: fcvtpu.2s v0, v0 162 ;CHECK-NEXT: ret 163 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtpu.v2i32.v2f32(<2 x float> %A) 164 ret <2 x i32> %tmp3 165 } 166 167 define <4 x i32> @fcvtpu_4s(<4 x float> %A) nounwind { 168 ;CHECK-LABEL: fcvtpu_4s: 169 ;CHECK-NOT: ld1 170 ;CHECK: fcvtpu.4s v0, v0 171 ;CHECK-NEXT: ret 172 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtpu.v4i32.v4f32(<4 x float> %A) 173 ret <4 x i32> %tmp3 174 } 175 176 define <2 x i64> @fcvtpu_2d(<2 x double> %A) nounwind { 177 ;CHECK-LABEL: fcvtpu_2d: 178 ;CHECK-NOT: ld1 179 ;CHECK: fcvtpu.2d v0, v0 180 ;CHECK-NEXT: ret 181 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double> %A) 182 ret <2 x i64> %tmp3 183 } 184 185 declare <2 x i32> @llvm.aarch64.neon.fcvtpu.v2i32.v2f32(<2 x float>) nounwind readnone 186 declare <4 x i32> @llvm.aarch64.neon.fcvtpu.v4i32.v4f32(<4 x float>) nounwind readnone 187 declare <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double>) nounwind readnone 188 189 define <2 x i32> @fcvtns_2s(<2 x float> %A) nounwind { 190 ;CHECK-LABEL: fcvtns_2s: 191 ;CHECK-NOT: ld1 192 ;CHECK: fcvtns.2s v0, v0 193 ;CHECK-NEXT: ret 194 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtns.v2i32.v2f32(<2 x float> %A) 195 ret <2 x i32> %tmp3 196 } 197 198 define <4 x i32> @fcvtns_4s(<4 x float> %A) nounwind { 199 ;CHECK-LABEL: fcvtns_4s: 200 ;CHECK-NOT: ld1 201 ;CHECK: fcvtns.4s v0, v0 202 ;CHECK-NEXT: ret 203 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtns.v4i32.v4f32(<4 x float> %A) 204 ret <4 x i32> %tmp3 205 } 206 207 define <2 x i64> @fcvtns_2d(<2 x double> %A) nounwind { 208 ;CHECK-LABEL: fcvtns_2d: 209 ;CHECK-NOT: ld1 210 ;CHECK: fcvtns.2d v0, v0 211 ;CHECK-NEXT: ret 212 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtns.v2i64.v2f64(<2 x double> %A) 213 ret <2 x i64> %tmp3 214 } 215 216 declare <2 x i32> @llvm.aarch64.neon.fcvtns.v2i32.v2f32(<2 x float>) nounwind readnone 217 declare <4 x i32> @llvm.aarch64.neon.fcvtns.v4i32.v4f32(<4 x float>) nounwind readnone 218 declare <2 x i64> @llvm.aarch64.neon.fcvtns.v2i64.v2f64(<2 x double>) nounwind readnone 219 220 define <2 x i32> @fcvtnu_2s(<2 x float> %A) nounwind { 221 ;CHECK-LABEL: fcvtnu_2s: 222 ;CHECK-NOT: ld1 223 ;CHECK: fcvtnu.2s v0, v0 224 ;CHECK-NEXT: ret 225 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float> %A) 226 ret <2 x i32> %tmp3 227 } 228 229 define <4 x i32> @fcvtnu_4s(<4 x float> %A) nounwind { 230 ;CHECK-LABEL: fcvtnu_4s: 231 ;CHECK-NOT: ld1 232 ;CHECK: fcvtnu.4s v0, v0 233 ;CHECK-NEXT: ret 234 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float> %A) 235 ret <4 x i32> %tmp3 236 } 237 238 define <2 x i64> @fcvtnu_2d(<2 x double> %A) nounwind { 239 ;CHECK-LABEL: fcvtnu_2d: 240 ;CHECK-NOT: ld1 241 ;CHECK: fcvtnu.2d v0, v0 242 ;CHECK-NEXT: ret 243 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double> %A) 244 ret <2 x i64> %tmp3 245 } 246 247 declare <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float>) nounwind readnone 248 declare <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float>) nounwind readnone 249 declare <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double>) nounwind readnone 250 251 define <2 x i32> @fcvtzs_2s(<2 x float> %A) nounwind { 252 ;CHECK-LABEL: fcvtzs_2s: 253 ;CHECK-NOT: ld1 254 ;CHECK: fcvtzs.2s v0, v0 255 ;CHECK-NEXT: ret 256 %tmp3 = fptosi <2 x float> %A to <2 x i32> 257 ret <2 x i32> %tmp3 258 } 259 260 define <4 x i32> @fcvtzs_4s(<4 x float> %A) nounwind { 261 ;CHECK-LABEL: fcvtzs_4s: 262 ;CHECK-NOT: ld1 263 ;CHECK: fcvtzs.4s v0, v0 264 ;CHECK-NEXT: ret 265 %tmp3 = fptosi <4 x float> %A to <4 x i32> 266 ret <4 x i32> %tmp3 267 } 268 269 define <2 x i64> @fcvtzs_2d(<2 x double> %A) nounwind { 270 ;CHECK-LABEL: fcvtzs_2d: 271 ;CHECK-NOT: ld1 272 ;CHECK: fcvtzs.2d v0, v0 273 ;CHECK-NEXT: ret 274 %tmp3 = fptosi <2 x double> %A to <2 x i64> 275 ret <2 x i64> %tmp3 276 } 277 278 279 define <2 x i32> @fcvtzu_2s(<2 x float> %A) nounwind { 280 ;CHECK-LABEL: fcvtzu_2s: 281 ;CHECK-NOT: ld1 282 ;CHECK: fcvtzu.2s v0, v0 283 ;CHECK-NEXT: ret 284 %tmp3 = fptoui <2 x float> %A to <2 x i32> 285 ret <2 x i32> %tmp3 286 } 287 288 define <4 x i32> @fcvtzu_4s(<4 x float> %A) nounwind { 289 ;CHECK-LABEL: fcvtzu_4s: 290 ;CHECK-NOT: ld1 291 ;CHECK: fcvtzu.4s v0, v0 292 ;CHECK-NEXT: ret 293 %tmp3 = fptoui <4 x float> %A to <4 x i32> 294 ret <4 x i32> %tmp3 295 } 296 297 define <2 x i64> @fcvtzu_2d(<2 x double> %A) nounwind { 298 ;CHECK-LABEL: fcvtzu_2d: 299 ;CHECK-NOT: ld1 300 ;CHECK: fcvtzu.2d v0, v0 301 ;CHECK-NEXT: ret 302 %tmp3 = fptoui <2 x double> %A to <2 x i64> 303 ret <2 x i64> %tmp3 304 } 305 306 define <2 x float> @frinta_2s(<2 x float> %A) nounwind { 307 ;CHECK-LABEL: frinta_2s: 308 ;CHECK-NOT: ld1 309 ;CHECK: frinta.2s v0, v0 310 ;CHECK-NEXT: ret 311 %tmp3 = call <2 x float> @llvm.round.v2f32(<2 x float> %A) 312 ret <2 x float> %tmp3 313 } 314 315 define <4 x float> @frinta_4s(<4 x float> %A) nounwind { 316 ;CHECK-LABEL: frinta_4s: 317 ;CHECK-NOT: ld1 318 ;CHECK: frinta.4s v0, v0 319 ;CHECK-NEXT: ret 320 %tmp3 = call <4 x float> @llvm.round.v4f32(<4 x float> %A) 321 ret <4 x float> %tmp3 322 } 323 324 define <2 x double> @frinta_2d(<2 x double> %A) nounwind { 325 ;CHECK-LABEL: frinta_2d: 326 ;CHECK-NOT: ld1 327 ;CHECK: frinta.2d v0, v0 328 ;CHECK-NEXT: ret 329 %tmp3 = call <2 x double> @llvm.round.v2f64(<2 x double> %A) 330 ret <2 x double> %tmp3 331 } 332 333 declare <2 x float> @llvm.round.v2f32(<2 x float>) nounwind readnone 334 declare <4 x float> @llvm.round.v4f32(<4 x float>) nounwind readnone 335 declare <2 x double> @llvm.round.v2f64(<2 x double>) nounwind readnone 336 337 define <2 x float> @frinti_2s(<2 x float> %A) nounwind { 338 ;CHECK-LABEL: frinti_2s: 339 ;CHECK-NOT: ld1 340 ;CHECK: frinti.2s v0, v0 341 ;CHECK-NEXT: ret 342 %tmp3 = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %A) 343 ret <2 x float> %tmp3 344 } 345 346 define <4 x float> @frinti_4s(<4 x float> %A) nounwind { 347 ;CHECK-LABEL: frinti_4s: 348 ;CHECK-NOT: ld1 349 ;CHECK: frinti.4s v0, v0 350 ;CHECK-NEXT: ret 351 %tmp3 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %A) 352 ret <4 x float> %tmp3 353 } 354 355 define <2 x double> @frinti_2d(<2 x double> %A) nounwind { 356 ;CHECK-LABEL: frinti_2d: 357 ;CHECK-NOT: ld1 358 ;CHECK: frinti.2d v0, v0 359 ;CHECK-NEXT: ret 360 %tmp3 = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %A) 361 ret <2 x double> %tmp3 362 } 363 364 declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) nounwind readnone 365 declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) nounwind readnone 366 declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) nounwind readnone 367 368 define <2 x float> @frintm_2s(<2 x float> %A) nounwind { 369 ;CHECK-LABEL: frintm_2s: 370 ;CHECK-NOT: ld1 371 ;CHECK: frintm.2s v0, v0 372 ;CHECK-NEXT: ret 373 %tmp3 = call <2 x float> @llvm.floor.v2f32(<2 x float> %A) 374 ret <2 x float> %tmp3 375 } 376 377 define <4 x float> @frintm_4s(<4 x float> %A) nounwind { 378 ;CHECK-LABEL: frintm_4s: 379 ;CHECK-NOT: ld1 380 ;CHECK: frintm.4s v0, v0 381 ;CHECK-NEXT: ret 382 %tmp3 = call <4 x float> @llvm.floor.v4f32(<4 x float> %A) 383 ret <4 x float> %tmp3 384 } 385 386 define <2 x double> @frintm_2d(<2 x double> %A) nounwind { 387 ;CHECK-LABEL: frintm_2d: 388 ;CHECK-NOT: ld1 389 ;CHECK: frintm.2d v0, v0 390 ;CHECK-NEXT: ret 391 %tmp3 = call <2 x double> @llvm.floor.v2f64(<2 x double> %A) 392 ret <2 x double> %tmp3 393 } 394 395 declare <2 x float> @llvm.floor.v2f32(<2 x float>) nounwind readnone 396 declare <4 x float> @llvm.floor.v4f32(<4 x float>) nounwind readnone 397 declare <2 x double> @llvm.floor.v2f64(<2 x double>) nounwind readnone 398 399 define <2 x float> @frintn_2s(<2 x float> %A) nounwind { 400 ;CHECK-LABEL: frintn_2s: 401 ;CHECK-NOT: ld1 402 ;CHECK: frintn.2s v0, v0 403 ;CHECK-NEXT: ret 404 %tmp3 = call <2 x float> @llvm.aarch64.neon.frintn.v2f32(<2 x float> %A) 405 ret <2 x float> %tmp3 406 } 407 408 define <4 x float> @frintn_4s(<4 x float> %A) nounwind { 409 ;CHECK-LABEL: frintn_4s: 410 ;CHECK-NOT: ld1 411 ;CHECK: frintn.4s v0, v0 412 ;CHECK-NEXT: ret 413 %tmp3 = call <4 x float> @llvm.aarch64.neon.frintn.v4f32(<4 x float> %A) 414 ret <4 x float> %tmp3 415 } 416 417 define <2 x double> @frintn_2d(<2 x double> %A) nounwind { 418 ;CHECK-LABEL: frintn_2d: 419 ;CHECK-NOT: ld1 420 ;CHECK: frintn.2d v0, v0 421 ;CHECK-NEXT: ret 422 %tmp3 = call <2 x double> @llvm.aarch64.neon.frintn.v2f64(<2 x double> %A) 423 ret <2 x double> %tmp3 424 } 425 426 declare <2 x float> @llvm.aarch64.neon.frintn.v2f32(<2 x float>) nounwind readnone 427 declare <4 x float> @llvm.aarch64.neon.frintn.v4f32(<4 x float>) nounwind readnone 428 declare <2 x double> @llvm.aarch64.neon.frintn.v2f64(<2 x double>) nounwind readnone 429 430 define <2 x float> @frintp_2s(<2 x float> %A) nounwind { 431 ;CHECK-LABEL: frintp_2s: 432 ;CHECK-NOT: ld1 433 ;CHECK: frintp.2s v0, v0 434 ;CHECK-NEXT: ret 435 %tmp3 = call <2 x float> @llvm.ceil.v2f32(<2 x float> %A) 436 ret <2 x float> %tmp3 437 } 438 439 define <4 x float> @frintp_4s(<4 x float> %A) nounwind { 440 ;CHECK-LABEL: frintp_4s: 441 ;CHECK-NOT: ld1 442 ;CHECK: frintp.4s v0, v0 443 ;CHECK-NEXT: ret 444 %tmp3 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %A) 445 ret <4 x float> %tmp3 446 } 447 448 define <2 x double> @frintp_2d(<2 x double> %A) nounwind { 449 ;CHECK-LABEL: frintp_2d: 450 ;CHECK-NOT: ld1 451 ;CHECK: frintp.2d v0, v0 452 ;CHECK-NEXT: ret 453 %tmp3 = call <2 x double> @llvm.ceil.v2f64(<2 x double> %A) 454 ret <2 x double> %tmp3 455 } 456 457 declare <2 x float> @llvm.ceil.v2f32(<2 x float>) nounwind readnone 458 declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone 459 declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone 460 461 define <2 x float> @frintx_2s(<2 x float> %A) nounwind { 462 ;CHECK-LABEL: frintx_2s: 463 ;CHECK-NOT: ld1 464 ;CHECK: frintx.2s v0, v0 465 ;CHECK-NEXT: ret 466 %tmp3 = call <2 x float> @llvm.rint.v2f32(<2 x float> %A) 467 ret <2 x float> %tmp3 468 } 469 470 define <4 x float> @frintx_4s(<4 x float> %A) nounwind { 471 ;CHECK-LABEL: frintx_4s: 472 ;CHECK-NOT: ld1 473 ;CHECK: frintx.4s v0, v0 474 ;CHECK-NEXT: ret 475 %tmp3 = call <4 x float> @llvm.rint.v4f32(<4 x float> %A) 476 ret <4 x float> %tmp3 477 } 478 479 define <2 x double> @frintx_2d(<2 x double> %A) nounwind { 480 ;CHECK-LABEL: frintx_2d: 481 ;CHECK-NOT: ld1 482 ;CHECK: frintx.2d v0, v0 483 ;CHECK-NEXT: ret 484 %tmp3 = call <2 x double> @llvm.rint.v2f64(<2 x double> %A) 485 ret <2 x double> %tmp3 486 } 487 488 declare <2 x float> @llvm.rint.v2f32(<2 x float>) nounwind readnone 489 declare <4 x float> @llvm.rint.v4f32(<4 x float>) nounwind readnone 490 declare <2 x double> @llvm.rint.v2f64(<2 x double>) nounwind readnone 491 492 define <2 x float> @frintz_2s(<2 x float> %A) nounwind { 493 ;CHECK-LABEL: frintz_2s: 494 ;CHECK-NOT: ld1 495 ;CHECK: frintz.2s v0, v0 496 ;CHECK-NEXT: ret 497 %tmp3 = call <2 x float> @llvm.trunc.v2f32(<2 x float> %A) 498 ret <2 x float> %tmp3 499 } 500 501 define <4 x float> @frintz_4s(<4 x float> %A) nounwind { 502 ;CHECK-LABEL: frintz_4s: 503 ;CHECK-NOT: ld1 504 ;CHECK: frintz.4s v0, v0 505 ;CHECK-NEXT: ret 506 %tmp3 = call <4 x float> @llvm.trunc.v4f32(<4 x float> %A) 507 ret <4 x float> %tmp3 508 } 509 510 define <2 x double> @frintz_2d(<2 x double> %A) nounwind { 511 ;CHECK-LABEL: frintz_2d: 512 ;CHECK-NOT: ld1 513 ;CHECK: frintz.2d v0, v0 514 ;CHECK-NEXT: ret 515 %tmp3 = call <2 x double> @llvm.trunc.v2f64(<2 x double> %A) 516 ret <2 x double> %tmp3 517 } 518 519 declare <2 x float> @llvm.trunc.v2f32(<2 x float>) nounwind readnone 520 declare <4 x float> @llvm.trunc.v4f32(<4 x float>) nounwind readnone 521 declare <2 x double> @llvm.trunc.v2f64(<2 x double>) nounwind readnone 522 523 define <2 x float> @fcvtxn_2s(<2 x double> %A) nounwind { 524 ;CHECK-LABEL: fcvtxn_2s: 525 ;CHECK-NOT: ld1 526 ;CHECK: fcvtxn v0.2s, v0.2d 527 ;CHECK-NEXT: ret 528 %tmp3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A) 529 ret <2 x float> %tmp3 530 } 531 532 define <4 x float> @fcvtxn_4s(<2 x float> %ret, <2 x double> %A) nounwind { 533 ;CHECK-LABEL: fcvtxn_4s: 534 ;CHECK-NOT: ld1 535 ;CHECK: fcvtxn2 v0.4s, v1.2d 536 ;CHECK-NEXT: ret 537 %tmp3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A) 538 %res = shufflevector <2 x float> %ret, <2 x float> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 539 ret <4 x float> %res 540 } 541 542 declare <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone 543 544 define <2 x i32> @fcvtzsc_2s(<2 x float> %A) nounwind { 545 ;CHECK-LABEL: fcvtzsc_2s: 546 ;CHECK-NOT: ld1 547 ;CHECK: fcvtzs.2s v0, v0, #1 548 ;CHECK-NEXT: ret 549 %tmp3 = call <2 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %A, i32 1) 550 ret <2 x i32> %tmp3 551 } 552 553 define <4 x i32> @fcvtzsc_4s(<4 x float> %A) nounwind { 554 ;CHECK-LABEL: fcvtzsc_4s: 555 ;CHECK-NOT: ld1 556 ;CHECK: fcvtzs.4s v0, v0, #1 557 ;CHECK-NEXT: ret 558 %tmp3 = call <4 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %A, i32 1) 559 ret <4 x i32> %tmp3 560 } 561 562 define <2 x i64> @fcvtzsc_2d(<2 x double> %A) nounwind { 563 ;CHECK-LABEL: fcvtzsc_2d: 564 ;CHECK-NOT: ld1 565 ;CHECK: fcvtzs.2d v0, v0, #1 566 ;CHECK-NEXT: ret 567 %tmp3 = call <2 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64(<2 x double> %A, i32 1) 568 ret <2 x i64> %tmp3 569 } 570 571 declare <2 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32) nounwind readnone 572 declare <4 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone 573 declare <2 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64(<2 x double>, i32) nounwind readnone 574 575 define <2 x i32> @fcvtzuc_2s(<2 x float> %A) nounwind { 576 ;CHECK-LABEL: fcvtzuc_2s: 577 ;CHECK-NOT: ld1 578 ;CHECK: fcvtzu.2s v0, v0, #1 579 ;CHECK-NEXT: ret 580 %tmp3 = call <2 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %A, i32 1) 581 ret <2 x i32> %tmp3 582 } 583 584 define <4 x i32> @fcvtzuc_4s(<4 x float> %A) nounwind { 585 ;CHECK-LABEL: fcvtzuc_4s: 586 ;CHECK-NOT: ld1 587 ;CHECK: fcvtzu.4s v0, v0, #1 588 ;CHECK-NEXT: ret 589 %tmp3 = call <4 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %A, i32 1) 590 ret <4 x i32> %tmp3 591 } 592 593 define <2 x i64> @fcvtzuc_2d(<2 x double> %A) nounwind { 594 ;CHECK-LABEL: fcvtzuc_2d: 595 ;CHECK-NOT: ld1 596 ;CHECK: fcvtzu.2d v0, v0, #1 597 ;CHECK-NEXT: ret 598 %tmp3 = call <2 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64(<2 x double> %A, i32 1) 599 ret <2 x i64> %tmp3 600 } 601 602 declare <2 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwind readnone 603 declare <4 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone 604 declare <2 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64(<2 x double>, i32) nounwind readnone 605 606 define <2 x float> @scvtf_2sc(<2 x i32> %A) nounwind { 607 ;CHECK-LABEL: scvtf_2sc: 608 ;CHECK-NOT: ld1 609 ;CHECK: scvtf.2s v0, v0, #1 610 ;CHECK-NEXT: ret 611 %tmp3 = call <2 x float> @llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %A, i32 1) 612 ret <2 x float> %tmp3 613 } 614 615 define <4 x float> @scvtf_4sc(<4 x i32> %A) nounwind { 616 ;CHECK-LABEL: scvtf_4sc: 617 ;CHECK-NOT: ld1 618 ;CHECK: scvtf.4s v0, v0, #1 619 ;CHECK-NEXT: ret 620 %tmp3 = call <4 x float> @llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %A, i32 1) 621 ret <4 x float> %tmp3 622 } 623 624 define <2 x double> @scvtf_2dc(<2 x i64> %A) nounwind { 625 ;CHECK-LABEL: scvtf_2dc: 626 ;CHECK-NOT: ld1 627 ;CHECK: scvtf.2d v0, v0, #1 628 ;CHECK-NEXT: ret 629 %tmp3 = call <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64> %A, i32 1) 630 ret <2 x double> %tmp3 631 } 632 633 declare <2 x float> @llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone 634 declare <4 x float> @llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone 635 declare <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone 636 637 define <2 x float> @ucvtf_2sc(<2 x i32> %A) nounwind { 638 ;CHECK-LABEL: ucvtf_2sc: 639 ;CHECK-NOT: ld1 640 ;CHECK: ucvtf.2s v0, v0, #1 641 ;CHECK-NEXT: ret 642 %tmp3 = call <2 x float> @llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %A, i32 1) 643 ret <2 x float> %tmp3 644 } 645 646 define <4 x float> @ucvtf_4sc(<4 x i32> %A) nounwind { 647 ;CHECK-LABEL: ucvtf_4sc: 648 ;CHECK-NOT: ld1 649 ;CHECK: ucvtf.4s v0, v0, #1 650 ;CHECK-NEXT: ret 651 %tmp3 = call <4 x float> @llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %A, i32 1) 652 ret <4 x float> %tmp3 653 } 654 655 define <2 x double> @ucvtf_2dc(<2 x i64> %A) nounwind { 656 ;CHECK-LABEL: ucvtf_2dc: 657 ;CHECK-NOT: ld1 658 ;CHECK: ucvtf.2d v0, v0, #1 659 ;CHECK-NEXT: ret 660 %tmp3 = call <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64> %A, i32 1) 661 ret <2 x double> %tmp3 662 } 663 664 665 ;CHECK-LABEL: autogen_SD28458: 666 ;CHECK: fcvt 667 ;CHECK: ret 668 define void @autogen_SD28458(<8 x double> %val.f64, <8 x float>* %addr.f32) { 669 %Tr53 = fptrunc <8 x double> %val.f64 to <8 x float> 670 store <8 x float> %Tr53, <8 x float>* %addr.f32 671 ret void 672 } 673 674 ;CHECK-LABEL: autogen_SD19225: 675 ;CHECK: fcvt 676 ;CHECK: ret 677 define void @autogen_SD19225(<8 x double>* %addr.f64, <8 x float>* %addr.f32) { 678 %A = load <8 x float>, <8 x float>* %addr.f32 679 %Tr53 = fpext <8 x float> %A to <8 x double> 680 store <8 x double> %Tr53, <8 x double>* %addr.f64 681 ret void 682 } 683 684 declare <2 x float> @llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone 685 declare <4 x float> @llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone 686 declare <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone 687
