1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s 2 ; RUN: llc < %s -O0 -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s 3 4 define <2 x double> @test_vcvt_f64_f32(<2 x float> %x) nounwind readnone ssp { 5 ; CHECK-LABEL: test_vcvt_f64_f32: 6 %vcvt1.i = fpext <2 x float> %x to <2 x double> 7 ; CHECK: fcvtl v0.2d, v0.2s 8 ret <2 x double> %vcvt1.i 9 ; CHECK: ret 10 } 11 12 define <2 x double> @test_vcvt_high_f64_f32(<4 x float> %x) nounwind readnone ssp { 13 ; CHECK-LABEL: test_vcvt_high_f64_f32: 14 %cvt_in = shufflevector <4 x float> %x, <4 x float> undef, <2 x i32> <i32 2, i32 3> 15 %vcvt1.i = fpext <2 x float> %cvt_in to <2 x double> 16 ; CHECK: fcvtl2 v0.2d, v0.4s 17 ret <2 x double> %vcvt1.i 18 ; CHECK: ret 19 } 20 21 define <2 x float> @test_vcvt_f32_f64(<2 x double> %v) nounwind readnone ssp { 22 ; CHECK-LABEL: test_vcvt_f32_f64: 23 %vcvt1.i = fptrunc <2 x double> %v to <2 x float> 24 ; CHECK: fcvtn 25 ret <2 x float> %vcvt1.i 26 ; CHECK: ret 27 } 28 29 define <4 x float> @test_vcvt_high_f32_f64(<2 x float> %x, <2 x double> %v) nounwind readnone ssp { 30 ; CHECK-LABEL: test_vcvt_high_f32_f64: 31 32 %cvt = fptrunc <2 x double> %v to <2 x float> 33 %vcvt2.i = shufflevector <2 x float> %x, <2 x float> %cvt, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 34 ; CHECK: fcvtn2 35 ret <4 x float> %vcvt2.i 36 ; CHECK: ret 37 } 38 39 define <2 x float> @test_vcvtx_f32_f64(<2 x double> %v) nounwind readnone ssp { 40 ; CHECK-LABEL: test_vcvtx_f32_f64: 41 %vcvtx1.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind 42 ; CHECK: fcvtxn 43 ret <2 x float> %vcvtx1.i 44 ; CHECK: ret 45 } 46 47 define <4 x float> @test_vcvtx_high_f32_f64(<2 x float> %x, <2 x double> %v) nounwind readnone ssp { 48 ; CHECK-LABEL: test_vcvtx_high_f32_f64: 49 %vcvtx2.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind 50 %res = shufflevector <2 x float> %x, <2 x float> %vcvtx2.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 51 ; CHECK: fcvtxn2 52 ret <4 x float> %res 53 ; CHECK: ret 54 } 55 56 57 declare <2 x double> @llvm.aarch64.neon.vcvthighfp2df(<4 x float>) nounwind readnone 58 declare <2 x double> @llvm.aarch64.neon.vcvtfp2df(<2 x float>) nounwind readnone 59 60 declare <2 x float> @llvm.aarch64.neon.vcvtdf2fp(<2 x double>) nounwind readnone 61 declare <4 x float> @llvm.aarch64.neon.vcvthighdf2fp(<2 x float>, <2 x double>) nounwind readnone 62 63 declare <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone 64 65 define i16 @to_half(float %in) { 66 ; CHECK-LABEL: to_half: 67 ; CHECK: fcvt h[[HALFVAL:[0-9]+]], s0 68 ; CHECK: fmov {{w[0-9]+}}, {{s[0-9]+}} 69 %res = call i16 @llvm.convert.to.fp16.f32(float %in) 70 ret i16 %res 71 } 72 73 define float @from_half(i16 %in) { 74 ; CHECK-LABEL: from_half: 75 ; CHECK: fmov {{s[0-9]+}}, {{w[0-9]+}} 76 ; CHECK: fcvt s0, {{h[0-9]+}} 77 %res = call float @llvm.convert.from.fp16.f32(i16 %in) 78 ret float %res 79 } 80 81 declare float @llvm.convert.from.fp16.f32(i16) #1 82 declare i16 @llvm.convert.to.fp16.f32(float) #1 83
