Home | History | Annotate | Download | only in AArch64 
      1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
      2 
      3 define <8 x i8> @and8xi8(<8 x i8> %a, <8 x i8> %b) {
      4 ; CHECK-LABEL: and8xi8:
      5 ; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
      6 	%tmp1 = and <8 x i8> %a, %b;
      7 	ret <8 x i8> %tmp1
      8 }
      9 
     10 define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) {
     11 ; CHECK-LABEL: and16xi8:
     12 ; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
     13 	%tmp1 = and <16 x i8> %a, %b;
     14 	ret <16 x i8> %tmp1
     15 }
     16 
     17 
     18 define <8 x i8> @orr8xi8(<8 x i8> %a, <8 x i8> %b) {
     19 ; CHECK-LABEL: orr8xi8:
     20 ; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
     21 	%tmp1 = or <8 x i8> %a, %b;
     22 	ret <8 x i8> %tmp1
     23 }
     24 
     25 define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) {
     26 ; CHECK-LABEL: orr16xi8:
     27 ; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
     28 	%tmp1 = or <16 x i8> %a, %b;
     29 	ret <16 x i8> %tmp1
     30 }
     31 
     32 
     33 define <8 x i8> @xor8xi8(<8 x i8> %a, <8 x i8> %b) {
     34 ; CHECK-LABEL: xor8xi8:
     35 ; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
     36 	%tmp1 = xor <8 x i8> %a, %b;
     37 	ret <8 x i8> %tmp1
     38 }
     39 
     40 define <16 x i8> @xor16xi8(<16 x i8> %a, <16 x i8> %b) {
     41 ; CHECK-LABEL: xor16xi8:
     42 ; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
     43 	%tmp1 = xor <16 x i8> %a, %b;
     44 	ret <16 x i8> %tmp1
     45 }
     46 
     47 define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b)  {
     48 ; CHECK-LABEL: bsl8xi8_const:
     49 ; CHECK:  bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
     50 	%tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0 >
     51 	%tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1 >
     52 	%tmp3 = or <8 x i8> %tmp1, %tmp2
     53 	ret <8 x i8> %tmp3
     54 }
     55 
     56 define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) {
     57 ; CHECK-LABEL: bsl16xi8_const:
     58 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
     59 	%tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0 >
     60 	%tmp2 = and <16 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1 >
     61 	%tmp3 = or <16 x i8> %tmp1, %tmp2
     62 	ret <16 x i8> %tmp3
     63 }
     64 
     65 define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b)  {
     66 ; CHECK-LABEL: orn8xi8:
     67 ; CHECK:  orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
     68   %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
     69   %tmp2 = or <8 x i8> %a, %tmp1
     70   ret <8 x i8> %tmp2
     71 }
     72 
     73 define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) {
     74 ; CHECK-LABEL: orn16xi8:
     75 ; CHECK:  orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
     76   %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
     77   %tmp2 = or <16 x i8> %a, %tmp1
     78   ret <16 x i8> %tmp2
     79 }
     80 
     81 define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b)  {
     82 ; CHECK-LABEL: bic8xi8:
     83 ; CHECK:  bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
     84   %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
     85   %tmp2 = and <8 x i8> %a, %tmp1
     86   ret <8 x i8> %tmp2
     87 }
     88 
     89 define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) {
     90 ; CHECK-LABEL: bic16xi8:
     91 ; CHECK:  bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
     92   %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
     93   %tmp2 = and <16 x i8> %a, %tmp1
     94   ret <16 x i8> %tmp2
     95 }
     96 
     97 define <2 x i32> @orrimm2s_lsl0(<2 x i32> %a) {
     98 ; CHECK-LABEL: orrimm2s_lsl0:
     99 ; CHECK:  orr {{v[0-9]+}}.2s, #{{0xff|255}}
    100 	%tmp1 = or <2 x i32> %a, < i32 255, i32 255>
    101 	ret <2 x i32> %tmp1
    102 }
    103 
    104 define <2 x i32> @orrimm2s_lsl8(<2 x i32> %a) {
    105 ; CHECK-LABEL: orrimm2s_lsl8:
    106 ; CHECK:  orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
    107 	%tmp1 = or <2 x i32> %a, < i32 65280, i32 65280>
    108 	ret <2 x i32> %tmp1
    109 }
    110 
    111 define <2 x i32> @orrimm2s_lsl16(<2 x i32> %a) {
    112 ; CHECK-LABEL: orrimm2s_lsl16:
    113 ; CHECK:  orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
    114 	%tmp1 = or <2 x i32> %a, < i32 16711680, i32 16711680>
    115 	ret <2 x i32> %tmp1
    116 }
    117 
    118 define <2 x i32> @orrimm2s_lsl24(<2 x i32> %a) {
    119 ; CHECK-LABEL: orrimm2s_lsl24:
    120 ; CHECK:  orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24
    121 	%tmp1 = or <2 x i32> %a, < i32 4278190080, i32 4278190080>
    122 	ret <2 x i32> %tmp1
    123 }
    124 
    125 define <4 x i32> @orrimm4s_lsl0(<4 x i32> %a) {
    126 ; CHECK-LABEL: orrimm4s_lsl0:
    127 ; CHECK:  orr {{v[0-9]+}}.4s, #{{0xff|255}}
    128 	%tmp1 = or <4 x i32> %a, < i32 255, i32 255, i32 255, i32 255>
    129 	ret <4 x i32> %tmp1
    130 }
    131 
    132 define <4 x i32> @orrimm4s_lsl8(<4 x i32> %a) {
    133 ; CHECK-LABEL: orrimm4s_lsl8:
    134 ; CHECK:  orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
    135 	%tmp1 = or <4 x i32> %a, < i32 65280, i32 65280, i32 65280, i32 65280>
    136 	ret <4 x i32> %tmp1
    137 }
    138 
    139 define <4 x i32> @orrimm4s_lsl16(<4 x i32> %a) {
    140 ; CHECK-LABEL: orrimm4s_lsl16:
    141 ; CHECK:  orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
    142 	%tmp1 = or <4 x i32> %a, < i32 16711680, i32 16711680, i32 16711680, i32 16711680>
    143 	ret <4 x i32> %tmp1
    144 }
    145 
    146 define <4 x i32> @orrimm4s_lsl24(<4 x i32> %a) {
    147 ; CHECK-LABEL: orrimm4s_lsl24:
    148 ; CHECK:  orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24
    149 	%tmp1 = or <4 x i32> %a, < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080>
    150 	ret <4 x i32> %tmp1
    151 }
    152 
    153 define <4 x i16> @orrimm4h_lsl0(<4 x i16> %a) {
    154 ; CHECK-LABEL: orrimm4h_lsl0:
    155 ; CHECK:  orr {{v[0-9]+}}.4h, #{{0xff|255}}
    156 	%tmp1 = or <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255 >
    157 	ret <4 x i16> %tmp1
    158 }
    159 
    160 define <4 x i16> @orrimm4h_lsl8(<4 x i16> %a) {
    161 ; CHECK-LABEL: orrimm4h_lsl8:
    162 ; CHECK:  orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
    163 	%tmp1 = or <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
    164 	ret <4 x i16> %tmp1
    165 }
    166 
    167 define <8 x i16> @orrimm8h_lsl0(<8 x i16> %a) {
    168 ; CHECK-LABEL: orrimm8h_lsl0:
    169 ; CHECK:  orr {{v[0-9]+}}.8h, #{{0xff|255}}
    170 	%tmp1 = or <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
    171 	ret <8 x i16> %tmp1
    172 }
    173 
    174 define <8 x i16> @orrimm8h_lsl8(<8 x i16> %a) {
    175 ; CHECK-LABEL: orrimm8h_lsl8:
    176 ; CHECK:  orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
    177 	%tmp1 = or <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
    178 	ret <8 x i16> %tmp1
    179 }
    180 
    181 define <2 x i32> @bicimm2s_lsl0(<2 x i32> %a) {
    182 ; CHECK-LABEL: bicimm2s_lsl0:
    183 ; CHECK:  bic {{v[0-9]+}}.2s, #{{0x10|16}}
    184 	%tmp1 = and <2 x i32> %a, < i32 4294967279, i32 4294967279 >
    185 	ret <2 x i32> %tmp1
    186 }
    187 
    188 define <2 x i32> @bicimm2s_lsl8(<2 x i32> %a) {
    189 ; CHECK-LABEL: bicimm2s_lsl8:
    190 ; CHECK:  bic {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #8
    191 	%tmp1 = and <2 x i32> %a, < i32 4294963199, i32  4294963199 >
    192 	ret <2 x i32> %tmp1
    193 }
    194 
    195 define <2 x i32> @bicimm2s_lsl16(<2 x i32> %a) {
    196 ; CHECK-LABEL: bicimm2s_lsl16:
    197 ; CHECK:  bic {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #16
    198 	%tmp1 = and <2 x i32> %a, < i32 4293918719, i32 4293918719 >
    199 	ret <2 x i32> %tmp1
    200 }
    201 
    202 define <2 x i32> @bicimm2s_lsl124(<2 x i32> %a) {
    203 ; CHECK-LABEL: bicimm2s_lsl124:
    204 ; CHECK:  bic {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #24
    205 	%tmp1 = and <2 x i32> %a, < i32 4026531839, i32  4026531839>
    206 	ret <2 x i32> %tmp1
    207 }
    208 
    209 define <4 x i32> @bicimm4s_lsl0(<4 x i32> %a) {
    210 ; CHECK-LABEL: bicimm4s_lsl0:
    211 ; CHECK:  bic {{v[0-9]+}}.4s, #{{0x10|16}}
    212 	%tmp1 = and <4 x i32> %a, < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
    213 	ret <4 x i32> %tmp1
    214 }
    215 
    216 define <4 x i32> @bicimm4s_lsl8(<4 x i32> %a) {
    217 ; CHECK-LABEL: bicimm4s_lsl8:
    218 ; CHECK:  bic {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #8
    219 	%tmp1 = and <4 x i32> %a, < i32 4294963199, i32  4294963199, i32  4294963199, i32  4294963199 >
    220 	ret <4 x i32> %tmp1
    221 }
    222 
    223 define <4 x i32> @bicimm4s_lsl16(<4 x i32> %a) {
    224 ; CHECK-LABEL: bicimm4s_lsl16:
    225 ; CHECK:  bic {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #16
    226 	%tmp1 = and <4 x i32> %a, < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
    227 	ret <4 x i32> %tmp1
    228 }
    229 
    230 define <4 x i32> @bicimm4s_lsl124(<4 x i32> %a) {
    231 ; CHECK-LABEL: bicimm4s_lsl124:
    232 ; CHECK:  bic {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #24
    233 	%tmp1 = and <4 x i32> %a, < i32 4026531839, i32  4026531839, i32  4026531839, i32  4026531839>
    234 	ret <4 x i32> %tmp1
    235 }
    236 
    237 define <4 x i16> @bicimm4h_lsl0_a(<4 x i16> %a) {
    238 ; CHECK-LABEL: bicimm4h_lsl0_a:
    239 ; CHECK:  bic {{v[0-9]+}}.4h, #{{0x10|16}}
    240 	%tmp1 = and <4 x i16> %a, < i16 4294967279, i16  4294967279, i16  4294967279, i16  4294967279 >
    241 	ret <4 x i16> %tmp1
    242 }
    243 
    244 define <4 x i16> @bicimm4h_lsl0_b(<4 x i16> %a) {
    245 ; CHECK-LABEL: bicimm4h_lsl0_b:
    246 ; CHECK:  bic {{v[0-9]+}}.4h, #{{0xff|255}}
    247 	%tmp1 = and <4 x i16> %a, < i16 65280, i16  65280, i16  65280, i16 65280 >
    248 	ret <4 x i16> %tmp1
    249 }
    250 
    251 define <4 x i16> @bicimm4h_lsl8_a(<4 x i16> %a) {
    252 ; CHECK-LABEL: bicimm4h_lsl8_a:
    253 ; CHECK:  bic {{v[0-9]+}}.4h, #{{0x10|16}}, lsl #8
    254 	%tmp1 = and <4 x i16> %a, < i16 4294963199, i16  4294963199, i16  4294963199, i16  4294963199>
    255 	ret <4 x i16> %tmp1
    256 }
    257 
    258 define <4 x i16> @bicimm4h_lsl8_b(<4 x i16> %a) {
    259 ; CHECK-LABEL: bicimm4h_lsl8_b:
    260 ; CHECK:  bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
    261 	%tmp1 = and <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255>
    262 	ret <4 x i16> %tmp1
    263 }
    264 
    265 define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) {
    266 ; CHECK-LABEL: bicimm8h_lsl0_a:
    267 ; CHECK:  bic {{v[0-9]+}}.8h, #{{0x10|16}}
    268 	%tmp1 = and <8 x i16> %a, < i16 4294967279, i16  4294967279, i16  4294967279, i16  4294967279,
    269    i16  4294967279, i16  4294967279, i16  4294967279, i16  4294967279 >
    270 	ret <8 x i16> %tmp1
    271 }
    272 
    273 define <8 x i16> @bicimm8h_lsl0_b(<8 x i16> %a) {
    274 ; CHECK-LABEL: bicimm8h_lsl0_b:
    275 ; CHECK:  bic {{v[0-9]+}}.8h, #{{0xff|255}}
    276 	%tmp1 = and <8 x i16> %a, < i16 65280, i16  65280, i16  65280, i16 65280, i16 65280, i16  65280, i16  65280, i16 65280 >
    277 	ret <8 x i16> %tmp1
    278 }
    279 
    280 define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) {
    281 ; CHECK-LABEL: bicimm8h_lsl8_a:
    282 ; CHECK:  bic {{v[0-9]+}}.8h, #{{0x10|16}}, lsl #8
    283 	%tmp1 = and <8 x i16> %a, < i16 4294963199, i16  4294963199, i16  4294963199, i16  4294963199,
    284    i16  4294963199, i16  4294963199, i16  4294963199, i16  4294963199>
    285 	ret <8 x i16> %tmp1
    286 }
    287 
    288 define <8 x i16> @bicimm8h_lsl8_b(<8 x i16> %a) {
    289 ; CHECK-LABEL: bicimm8h_lsl8_b:
    290 ; CHECK:  bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
    291 	%tmp1 = and <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
    292 	ret <8 x i16> %tmp1
    293 }
    294 
    295 define <2 x i32> @and2xi32(<2 x i32> %a, <2 x i32> %b) {
    296 ; CHECK-LABEL: and2xi32:
    297 ; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    298 	%tmp1 = and <2 x i32> %a, %b;
    299 	ret <2 x i32> %tmp1
    300 }
    301 
    302 define <4 x i16> @and4xi16(<4 x i16> %a, <4 x i16> %b) {
    303 ; CHECK-LABEL: and4xi16:
    304 ; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    305 	%tmp1 = and <4 x i16> %a, %b;
    306 	ret <4 x i16> %tmp1
    307 }
    308 
    309 define <1 x i64> @and1xi64(<1 x i64> %a, <1 x i64> %b) {
    310 ; CHECK-LABEL: and1xi64:
    311 ; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    312 	%tmp1 = and <1 x i64> %a, %b;
    313 	ret <1 x i64> %tmp1
    314 }
    315 
    316 define <4 x i32> @and4xi32(<4 x i32> %a, <4 x i32> %b) {
    317 ; CHECK-LABEL: and4xi32:
    318 ; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    319 	%tmp1 = and <4 x i32> %a, %b;
    320 	ret <4 x i32> %tmp1
    321 }
    322 
    323 define <8 x i16> @and8xi16(<8 x i16> %a, <8 x i16> %b) {
    324 ; CHECK-LABEL: and8xi16:
    325 ; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    326 	%tmp1 = and <8 x i16> %a, %b;
    327 	ret <8 x i16> %tmp1
    328 }
    329 
    330 define <2 x i64> @and2xi64(<2 x i64> %a, <2 x i64> %b) {
    331 ; CHECK-LABEL: and2xi64:
    332 ; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    333 	%tmp1 = and <2 x i64> %a, %b;
    334 	ret <2 x i64> %tmp1
    335 }
    336 
    337 define <2 x i32> @orr2xi32(<2 x i32> %a, <2 x i32> %b) {
    338 ; CHECK-LABEL: orr2xi32:
    339 ; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    340 	%tmp1 = or <2 x i32> %a, %b;
    341 	ret <2 x i32> %tmp1
    342 }
    343 
    344 define <4 x i16> @orr4xi16(<4 x i16> %a, <4 x i16> %b) {
    345 ; CHECK-LABEL: orr4xi16:
    346 ; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    347 	%tmp1 = or <4 x i16> %a, %b;
    348 	ret <4 x i16> %tmp1
    349 }
    350 
    351 define <1 x i64> @orr1xi64(<1 x i64> %a, <1 x i64> %b) {
    352 ; CHECK-LABEL: orr1xi64:
    353 ; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    354 	%tmp1 = or <1 x i64> %a, %b;
    355 	ret <1 x i64> %tmp1
    356 }
    357 
    358 define <4 x i32> @orr4xi32(<4 x i32> %a, <4 x i32> %b) {
    359 ; CHECK-LABEL: orr4xi32:
    360 ; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    361 	%tmp1 = or <4 x i32> %a, %b;
    362 	ret <4 x i32> %tmp1
    363 }
    364 
    365 define <8 x i16> @orr8xi16(<8 x i16> %a, <8 x i16> %b) {
    366 ; CHECK-LABEL: orr8xi16:
    367 ; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    368 	%tmp1 = or <8 x i16> %a, %b;
    369 	ret <8 x i16> %tmp1
    370 }
    371 
    372 define <2 x i64> @orr2xi64(<2 x i64> %a, <2 x i64> %b) {
    373 ; CHECK-LABEL: orr2xi64:
    374 ; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    375 	%tmp1 = or <2 x i64> %a, %b;
    376 	ret <2 x i64> %tmp1
    377 }
    378 
    379 define <2 x i32> @eor2xi32(<2 x i32> %a, <2 x i32> %b) {
    380 ; CHECK-LABEL: eor2xi32:
    381 ; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    382 	%tmp1 = xor <2 x i32> %a, %b;
    383 	ret <2 x i32> %tmp1
    384 }
    385 
    386 define <4 x i16> @eor4xi16(<4 x i16> %a, <4 x i16> %b) {
    387 ; CHECK-LABEL: eor4xi16:
    388 ; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    389 	%tmp1 = xor <4 x i16> %a, %b;
    390 	ret <4 x i16> %tmp1
    391 }
    392 
    393 define <1 x i64> @eor1xi64(<1 x i64> %a, <1 x i64> %b) {
    394 ; CHECK-LABEL: eor1xi64:
    395 ; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    396 	%tmp1 = xor <1 x i64> %a, %b;
    397 	ret <1 x i64> %tmp1
    398 }
    399 
    400 define <4 x i32> @eor4xi32(<4 x i32> %a, <4 x i32> %b) {
    401 ; CHECK-LABEL: eor4xi32:
    402 ; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    403 	%tmp1 = xor <4 x i32> %a, %b;
    404 	ret <4 x i32> %tmp1
    405 }
    406 
    407 define <8 x i16> @eor8xi16(<8 x i16> %a, <8 x i16> %b) {
    408 ; CHECK-LABEL: eor8xi16:
    409 ; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    410 	%tmp1 = xor <8 x i16> %a, %b;
    411 	ret <8 x i16> %tmp1
    412 }
    413 
    414 define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) {
    415 ; CHECK-LABEL: eor2xi64:
    416 ; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    417 	%tmp1 = xor <2 x i64> %a, %b;
    418 	ret <2 x i64> %tmp1
    419 }
    420 
    421 
    422 define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b)  {
    423 ; CHECK-LABEL: bic2xi32:
    424 ; CHECK:  bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    425   %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
    426   %tmp2 = and <2 x i32> %a, %tmp1
    427   ret <2 x i32> %tmp2
    428 }
    429 
    430 define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b)  {
    431 ; CHECK-LABEL: bic4xi16:
    432 ; CHECK:  bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    433   %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
    434   %tmp2 = and <4 x i16> %a, %tmp1
    435   ret <4 x i16> %tmp2
    436 }
    437 
    438 define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b)  {
    439 ; CHECK-LABEL: bic1xi64:
    440 ; CHECK:  bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    441   %tmp1 = xor <1 x i64> %b, < i64 -1>
    442   %tmp2 = and <1 x i64> %a, %tmp1
    443   ret <1 x i64> %tmp2
    444 }
    445 
    446 define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b)  {
    447 ; CHECK-LABEL: bic4xi32:
    448 ; CHECK:  bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    449   %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
    450   %tmp2 = and <4 x i32> %a, %tmp1
    451   ret <4 x i32> %tmp2
    452 }
    453 
    454 define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b)  {
    455 ; CHECK-LABEL: bic8xi16:
    456 ; CHECK:  bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    457   %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
    458   %tmp2 = and <8 x i16> %a, %tmp1
    459   ret <8 x i16> %tmp2
    460 }
    461 
    462 define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b)  {
    463 ; CHECK-LABEL: bic2xi64:
    464 ; CHECK:  bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    465   %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
    466   %tmp2 = and <2 x i64> %a, %tmp1
    467   ret <2 x i64> %tmp2
    468 }
    469 
    470 define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b)  {
    471 ; CHECK-LABEL: orn2xi32:
    472 ; CHECK:  orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    473   %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
    474   %tmp2 = or <2 x i32> %a, %tmp1
    475   ret <2 x i32> %tmp2
    476 }
    477 
    478 define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b)  {
    479 ; CHECK-LABEL: orn4xi16:
    480 ; CHECK:  orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    481   %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
    482   %tmp2 = or <4 x i16> %a, %tmp1
    483   ret <4 x i16> %tmp2
    484 }
    485 
    486 define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b)  {
    487 ; CHECK-LABEL: orn1xi64:
    488 ; CHECK:  orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    489   %tmp1 = xor <1 x i64> %b, < i64 -1>
    490   %tmp2 = or <1 x i64> %a, %tmp1
    491   ret <1 x i64> %tmp2
    492 }
    493 
    494 define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b)  {
    495 ; CHECK-LABEL: orn4xi32:
    496 ; CHECK:  orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    497   %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
    498   %tmp2 = or <4 x i32> %a, %tmp1
    499   ret <4 x i32> %tmp2
    500 }
    501 
    502 define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b)  {
    503 ; CHECK-LABEL: orn8xi16:
    504 ; CHECK:  orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    505   %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
    506   %tmp2 = or <8 x i16> %a, %tmp1
    507   ret <8 x i16> %tmp2
    508 }
    509 
    510 define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b)  {
    511 ; CHECK-LABEL: orn2xi64:
    512 ; CHECK:  orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    513   %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
    514   %tmp2 = or <2 x i64> %a, %tmp1
    515   ret <2 x i64> %tmp2
    516 }
    517 
    518 define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b)  {
    519 ; CHECK-LABEL: bsl2xi32_const:
    520 ; CHECK:  bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    521 	%tmp1 = and <2 x i32> %a, < i32 -1, i32 0 >
    522 	%tmp2 = and <2 x i32> %b, < i32 0, i32 -1 >
    523 	%tmp3 = or <2 x i32> %tmp1, %tmp2
    524 	ret <2 x i32> %tmp3
    525 }
    526 
    527 
    528 define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b)  {
    529 ; CHECK-LABEL: bsl4xi16_const:
    530 ; CHECK:  bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    531 	%tmp1 = and <4 x i16> %a, < i16 -1, i16 0, i16 -1,i16 0 >
    532 	%tmp2 = and <4 x i16> %b, < i16 0, i16 -1,i16 0, i16 -1 >
    533 	%tmp3 = or <4 x i16> %tmp1, %tmp2
    534 	ret <4 x i16> %tmp3
    535 }
    536 
    537 define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b)  {
    538 ; CHECK-LABEL: bsl1xi64_const:
    539 ; CHECK:  bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    540 	%tmp1 = and <1 x i64> %a, < i64 -16 >
    541 	%tmp2 = and <1 x i64> %b, < i64 15 >
    542 	%tmp3 = or <1 x i64> %tmp1, %tmp2
    543 	ret <1 x i64> %tmp3
    544 }
    545 
    546 define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b)  {
    547 ; CHECK-LABEL: bsl4xi32_const:
    548 ; CHECK:  bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    549 	%tmp1 = and <4 x i32> %a, < i32 -1, i32 0, i32 -1, i32 0 >
    550 	%tmp2 = and <4 x i32> %b, < i32 0, i32 -1, i32 0, i32 -1 >
    551 	%tmp3 = or <4 x i32> %tmp1, %tmp2
    552 	ret <4 x i32> %tmp3
    553 }
    554 
    555 define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b)  {
    556 ; CHECK-LABEL: bsl8xi16_const:
    557 ; CHECK:  bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    558 	%tmp1 = and <8 x i16> %a, < i16 -1, i16 -1, i16 0,i16 0, i16 -1, i16 -1, i16 0,i16 0 >
    559 	%tmp2 = and <8 x i16> %b, < i16 0, i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 -1, i16 -1 >
    560 	%tmp3 = or <8 x i16> %tmp1, %tmp2
    561 	ret <8 x i16> %tmp3
    562 }
    563 
    564 define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b)  {
    565 ; CHECK-LABEL: bsl2xi64_const:
    566 ; CHECK:  bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    567 	%tmp1 = and <2 x i64> %a, < i64 -1, i64 0 >
    568 	%tmp2 = and <2 x i64> %b, < i64 0, i64 -1 >
    569 	%tmp3 = or <2 x i64> %tmp1, %tmp2
    570 	ret <2 x i64> %tmp3
    571 }
    572 
    573 
    574 define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {
    575 ; CHECK-LABEL: bsl8xi8:
    576 ; CHECK:  bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    577   %1 = and <8 x i8> %v1, %v2
    578   %2 = xor <8 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
    579   %3 = and <8 x i8> %2, %v3
    580   %4 = or <8 x i8> %1, %3
    581   ret <8 x i8> %4
    582 }
    583 
    584 define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) {
    585 ; CHECK-LABEL: bsl4xi16:
    586 ; CHECK:  bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    587   %1 = and <4 x i16> %v1, %v2
    588   %2 = xor <4 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1>
    589   %3 = and <4 x i16> %2, %v3
    590   %4 = or <4 x i16> %1, %3
    591   ret <4 x i16> %4
    592 }
    593 
    594 define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {
    595 ; CHECK-LABEL: bsl2xi32:
    596 ; CHECK:  bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    597   %1 = and <2 x i32> %v1, %v2
    598   %2 = xor <2 x i32> %v1, <i32 -1, i32 -1>
    599   %3 = and <2 x i32> %2, %v3
    600   %4 = or <2 x i32> %1, %3
    601   ret <2 x i32> %4
    602 }
    603 
    604 define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
    605 ; CHECK-LABEL: bsl1xi64:
    606 ; CHECK:  bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    607   %1 = and <1 x i64> %v1, %v2
    608   %2 = xor <1 x i64> %v1, <i64 -1>
    609   %3 = and <1 x i64> %2, %v3
    610   %4 = or <1 x i64> %1, %3
    611   ret <1 x i64> %4
    612 }
    613 
    614 define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) {
    615 ; CHECK-LABEL: bsl16xi8:
    616 ; CHECK:  bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    617   %1 = and <16 x i8> %v1, %v2
    618   %2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
    619   %3 = and <16 x i8> %2, %v3
    620   %4 = or <16 x i8> %1, %3
    621   ret <16 x i8> %4
    622 }
    623 
    624 define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
    625 ; CHECK-LABEL: bsl8xi16:
    626 ; CHECK:  bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    627   %1 = and <8 x i16> %v1, %v2
    628   %2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
    629   %3 = and <8 x i16> %2, %v3
    630   %4 = or <8 x i16> %1, %3
    631   ret <8 x i16> %4
    632 }
    633 
    634 define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
    635 ; CHECK-LABEL: bsl4xi32:
    636 ; CHECK:  bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    637   %1 = and <4 x i32> %v1, %v2
    638   %2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
    639   %3 = and <4 x i32> %2, %v3
    640   %4 = or <4 x i32> %1, %3
    641   ret <4 x i32> %4
    642 }
    643 
    644 define <8 x i8> @vselect_v8i8(<8 x i8> %a) {
    645 ; CHECK-LABEL: vselect_v8i8:
    646 ; CHECK:  movi {{d[0-9]+}}, #0x{{0*}}ffff
    647 ; CHECK-NEXT:  {{bsl v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b|and v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b}}
    648   %b = select <8 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> <i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
    649   ret <8 x i8> %b
    650 }
    651 
    652 define <4 x i16> @vselect_v4i16(<4 x i16> %a) {
    653 ; CHECK-LABEL: vselect_v4i16:
    654 ; CHECK:  movi {{d[0-9]+}}, #0x{{0*}}ffff
    655 ; CHECK-NEXT:  {{bsl v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b|and v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b}}
    656   %b = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i16> %a, <4 x i16> <i16 undef, i16 0, i16 0, i16 0>
    657   ret <4 x i16> %b
    658 }
    659 
    660 define <8 x i8> @vselect_cmp_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
    661 ; CHECK-LABEL: vselect_cmp_ne:
    662 ; CHECK:  cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    663 ; CHECK-NEXT:  {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    664 ; CHECK-NEXT:  bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    665   %cmp = icmp ne <8 x i8> %a, %b
    666   %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
    667   ret <8 x i8> %d
    668 }
    669 
    670 define <8 x i8> @vselect_cmp_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
    671 ; CHECK-LABEL: vselect_cmp_eq:
    672 ; CHECK:  cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    673 ; CHECK-NEXT:  bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    674   %cmp = icmp eq <8 x i8> %a, %b
    675   %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
    676   ret <8 x i8> %d
    677 }
    678 
    679 define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
    680 ; CHECK-LABEL: vselect_cmpz_ne:
    681 ; CHECK:  cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
    682 ; CHECK-NEXT:  {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    683 ; CHECK-NEXT:  bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    684   %cmp = icmp ne <8 x i8> %a, zeroinitializer
    685   %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
    686   ret <8 x i8> %d
    687 }
    688 
    689 define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
    690 ; CHECK-LABEL: vselect_cmpz_eq:
    691 ; CHECK:  cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
    692 ; CHECK-NEXT:  bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    693   %cmp = icmp eq <8 x i8> %a, zeroinitializer
    694   %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
    695   ret <8 x i8> %d
    696 }
    697 
    698 define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
    699 ; CHECK-LABEL: vselect_tst:
    700 ; CHECK:  cmtst {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    701 ; CHECK-NEXT:  bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
    702 	%tmp3 = and <8 x i8> %a, %b
    703 	%tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
    704   %d = select <8 x i1> %tmp4, <8 x i8> %b, <8 x i8> %c
    705   ret <8 x i8> %d
    706 }
    707 
    708 define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) {
    709 ; CHECK-LABEL: bsl2xi64:
    710 ; CHECK:  bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
    711   %1 = and <2 x i64> %v1, %v2
    712   %2 = xor <2 x i64> %v1, <i64 -1, i64 -1>
    713   %3 = and <2 x i64> %2, %v3
    714   %4 = or <2 x i64> %1, %3
    715   ret <2 x i64> %4
    716 }
    717 
    718 define <8 x i8> @orrimm8b_as_orrimm4h_lsl0(<8 x i8> %a) {
    719 ; CHECK-LABEL: orrimm8b_as_orrimm4h_lsl0:
    720 ; CHECK:  orr {{v[0-9]+}}.4h, #{{0xff|255}}
    721   %val = or <8 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
    722   ret <8 x i8> %val
    723 }
    724 
    725 define <8 x i8> @orrimm8b_as_orimm4h_lsl8(<8 x i8> %a) {
    726 ; CHECK-LABEL: orrimm8b_as_orimm4h_lsl8:
    727 ; CHECK:  orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
    728   %val = or <8 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
    729   ret <8 x i8> %val
    730 }
    731 
    732 define <16 x i8> @orimm16b_as_orrimm8h_lsl0(<16 x i8> %a) {
    733 ; CHECK-LABEL: orimm16b_as_orrimm8h_lsl0:
    734 ; CHECK:  orr {{v[0-9]+}}.8h, #{{0xff|255}}
    735   %val = or <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
    736   ret <16 x i8> %val
    737 }
    738 
    739 define <16 x i8> @orimm16b_as_orrimm8h_lsl8(<16 x i8> %a) {
    740 ; CHECK-LABEL: orimm16b_as_orrimm8h_lsl8:
    741 ; CHECK:  orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
    742   %val = or <16 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
    743   ret <16 x i8> %val
    744 }
    745 
    746 define <8 x i8> @and8imm2s_lsl0(<8 x i8> %a) {
    747 ; CHECK-LABEL: and8imm2s_lsl0:
    748 ; CHECK:  bic {{v[0-9]+}}.2s, #{{0xff|255}}
    749 	%tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
    750 	ret <8 x i8> %tmp1
    751 }
    752 
    753 define <8 x i8> @and8imm2s_lsl8(<8 x i8> %a) {
    754 ; CHECK-LABEL: and8imm2s_lsl8:
    755 ; CHECK:  bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
    756 	%tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
    757 	ret <8 x i8> %tmp1
    758 }
    759 
    760 define <8 x i8> @and8imm2s_lsl16(<8 x i8> %a) {
    761 ; CHECK-LABEL: and8imm2s_lsl16:
    762 ; CHECK:  bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
    763 	%tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
    764 	ret <8 x i8> %tmp1
    765 }
    766 
    767 define <8 x i8> @and8imm2s_lsl24(<8 x i8> %a) {
    768 ; CHECK-LABEL: and8imm2s_lsl24:
    769 ; CHECK:  bic {{v[0-9]+}}.2s, #{{0xfe|254}}, lsl #24
    770 	%tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
    771 	ret <8 x i8> %tmp1
    772 }
    773 
    774 define <4 x i16> @and16imm2s_lsl0(<4 x i16> %a) {
    775 ; CHECK-LABEL: and16imm2s_lsl0:
    776 ; CHECK:  bic {{v[0-9]+}}.2s, #{{0xff|255}}
    777 	%tmp1 = and <4 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535>
    778 	ret <4 x i16> %tmp1
    779 }
    780 
    781 define <4 x i16> @and16imm2s_lsl8(<4 x i16> %a) {
    782 ; CHECK-LABEL: and16imm2s_lsl8:
    783 ; CHECK:  bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
    784 	%tmp1 = and <4 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535>
    785 	ret <4 x i16> %tmp1
    786 }
    787 
    788 define <4 x i16> @and16imm2s_lsl16(<4 x i16> %a) {
    789 ; CHECK-LABEL: and16imm2s_lsl16:
    790 ; CHECK:  bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
    791 	%tmp1 = and <4 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280>
    792 	ret <4 x i16> %tmp1
    793 }
    794 
    795 define <4 x i16> @and16imm2s_lsl24(<4 x i16> %a) {
    796 ; CHECK-LABEL: and16imm2s_lsl24:
    797 ; CHECK:  bic {{v[0-9]+}}.2s, #{{0xfe|254}}, lsl #24
    798 	%tmp1 = and <4 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511>
    799 	ret <4 x i16> %tmp1
    800 }
    801 
    802 
    803 define <1 x i64> @and64imm2s_lsl0(<1 x i64> %a) {
    804 ; CHECK-LABEL: and64imm2s_lsl0:
    805 ; CHECK:  bic {{v[0-9]+}}.2s, #{{0xff|255}}
    806 	%tmp1 = and <1 x i64> %a, < i64 -1095216660736>
    807 	ret <1 x i64> %tmp1
    808 }
    809 
    810 define <1 x i64> @and64imm2s_lsl8(<1 x i64> %a) {
    811 ; CHECK-LABEL: and64imm2s_lsl8:
    812 ; CHECK:  bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
    813 	%tmp1 = and <1 x i64> %a, < i64 -280375465148161>
    814 	ret <1 x i64> %tmp1
    815 }
    816 
    817 define <1 x i64> @and64imm2s_lsl16(<1 x i64> %a) {
    818 ; CHECK-LABEL: and64imm2s_lsl16:
    819 ; CHECK:  bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
    820 	%tmp1 = and <1 x i64> %a, < i64 -71776119077928961>
    821 	ret <1 x i64> %tmp1
    822 }
    823 
    824 define <1 x i64> @and64imm2s_lsl24(<1 x i64> %a) {
    825 ; CHECK-LABEL: and64imm2s_lsl24:
    826 ; CHECK:  bic {{v[0-9]+}}.2s, #{{0xfe|254}}, lsl #24
    827 	%tmp1 = and <1 x i64> %a, < i64 144115183814443007>
    828 	ret <1 x i64> %tmp1
    829 }
    830 
    831 define <16 x i8> @and8imm4s_lsl0(<16 x i8> %a) {
    832 ; CHECK-LABEL: and8imm4s_lsl0:
    833 ; CHECK:  bic {{v[0-9]+}}.4s, #{{0xff|255}}
    834 	%tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
    835 	ret <16 x i8> %tmp1
    836 }
    837 
    838 define <16 x i8> @and8imm4s_lsl8(<16 x i8> %a) {
    839 ; CHECK-LABEL: and8imm4s_lsl8:
    840 ; CHECK:  bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
    841 	%tmp1 = and <16 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
    842 	ret <16 x i8> %tmp1
    843 }
    844 
    845 define <16 x i8> @and8imm4s_lsl16(<16 x i8> %a) {
    846 ; CHECK-LABEL: and8imm4s_lsl16:
    847 ; CHECK:  bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
    848 	%tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
    849 	ret <16 x i8> %tmp1
    850 }
    851 
    852 define <16 x i8> @and8imm4s_lsl24(<16 x i8> %a) {
    853 ; CHECK-LABEL: and8imm4s_lsl24:
    854 ; CHECK:  bic {{v[0-9]+}}.4s, #{{0xfe|254}}, lsl #24
    855 	%tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
    856 	ret <16 x i8> %tmp1
    857 }
    858 
    859 define <8 x i16> @and16imm4s_lsl0(<8 x i16> %a) {
    860 ; CHECK-LABEL: and16imm4s_lsl0:
    861 ; CHECK:  bic {{v[0-9]+}}.4s, #{{0xff|255}}
    862 	%tmp1 = and <8 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535>
    863 	ret <8 x i16> %tmp1
    864 }
    865 
    866 define <8 x i16> @and16imm4s_lsl8(<8 x i16> %a) {
    867 ; CHECK-LABEL: and16imm4s_lsl8:
    868 ; CHECK:  bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
    869 	%tmp1 = and <8 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535>
    870 	ret <8 x i16> %tmp1
    871 }
    872 
    873 define <8 x i16> @and16imm4s_lsl16(<8 x i16> %a) {
    874 ; CHECK-LABEL: and16imm4s_lsl16:
    875 ; CHECK:  bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
    876 	%tmp1 = and <8 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280>
    877 	ret <8 x i16> %tmp1
    878 }
    879 
    880 define <8 x i16> @and16imm4s_lsl24(<8 x i16> %a) {
    881 ; CHECK-LABEL: and16imm4s_lsl24:
    882 ; CHECK:  bic {{v[0-9]+}}.4s, #{{0xfe|254}}, lsl #24
    883 	%tmp1 = and <8 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511>
    884 	ret <8 x i16> %tmp1
    885 }
    886 
    887 define <2 x i64> @and64imm4s_lsl0(<2 x i64> %a) {
    888 ; CHECK-LABEL: and64imm4s_lsl0:
    889 ; CHECK:  bic {{v[0-9]+}}.4s, #{{0xff|255}}
    890 	%tmp1 = and <2 x i64> %a, < i64 -1095216660736, i64 -1095216660736>
    891 	ret <2 x i64> %tmp1
    892 }
    893 
    894 define <2 x i64> @and64imm4s_lsl8(<2 x i64> %a) {
    895 ; CHECK-LABEL: and64imm4s_lsl8:
    896 ; CHECK:  bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
    897 	%tmp1 = and <2 x i64> %a, < i64 -280375465148161, i64 -280375465148161>
    898 	ret <2 x i64> %tmp1
    899 }
    900 
    901 define <2 x i64> @and64imm4s_lsl16(<2 x i64> %a) {
    902 ; CHECK-LABEL: and64imm4s_lsl16:
    903 ; CHECK:  bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
    904 	%tmp1 = and <2 x i64> %a, < i64 -71776119077928961, i64 -71776119077928961>
    905 	ret <2 x i64> %tmp1
    906 }
    907 
    908 define <2 x i64> @and64imm4s_lsl24(<2 x i64> %a) {
    909 ; CHECK-LABEL: and64imm4s_lsl24:
    910 ; CHECK:  bic {{v[0-9]+}}.4s, #{{0xfe|254}}, lsl #24
    911 	%tmp1 = and <2 x i64> %a, < i64 144115183814443007, i64 144115183814443007>
    912 	ret <2 x i64> %tmp1
    913 }
    914 
    915 define <8 x i8> @and8imm4h_lsl0(<8 x i8> %a) {
    916 ; CHECK-LABEL: and8imm4h_lsl0:
    917 ; CHECK:  bic {{v[0-9]+}}.4h, #{{0xff|255}}
    918 	%tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
    919 	ret <8 x i8> %tmp1
    920 }
    921 
    922 define <8 x i8> @and8imm4h_lsl8(<8 x i8> %a) {
    923 ; CHECK-LABEL: and8imm4h_lsl8:
    924 ; CHECK:  bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
    925 	%tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
    926 	ret <8 x i8> %tmp1
    927 }
    928 
    929 define <2 x i32> @and16imm4h_lsl0(<2 x i32> %a) {
    930 ; CHECK-LABEL: and16imm4h_lsl0:
    931 ; CHECK:  bic {{v[0-9]+}}.4h, #{{0xff|255}}
    932 	%tmp1 = and <2 x i32> %a, < i32 4278255360, i32 4278255360>
    933 	ret <2 x i32> %tmp1
    934 }
    935 
    936 define <2 x i32> @and16imm4h_lsl8(<2 x i32> %a) {
    937 ; CHECK-LABEL: and16imm4h_lsl8:
    938 ; CHECK:  bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
    939 	%tmp1 = and <2 x i32> %a, < i32 16711935, i32 16711935>
    940 	ret <2 x i32> %tmp1
    941 }
    942 
    943 define <1 x i64> @and64imm4h_lsl0(<1 x i64> %a) {
    944 ; CHECK-LABEL: and64imm4h_lsl0:
    945 ; CHECK:  bic {{v[0-9]+}}.4h, #{{0xff|255}}
    946 	%tmp1 = and <1 x i64> %a, < i64 -71777214294589696>
    947 	ret <1 x i64> %tmp1
    948 }
    949 
    950 define <1 x i64> @and64imm4h_lsl8(<1 x i64> %a) {
    951 ; CHECK-LABEL: and64imm4h_lsl8:
    952 ; CHECK:  bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
    953 	%tmp1 = and <1 x i64> %a, < i64 71777214294589695>
    954 	ret <1 x i64> %tmp1
    955 }
    956 
    957 define <16 x i8> @and8imm8h_lsl0(<16 x i8> %a) {
    958 ; CHECK-LABEL: and8imm8h_lsl0:
    959 ; CHECK:  bic {{v[0-9]+}}.8h, #{{0xff|255}}
    960 	%tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255 >
    961 	ret <16 x i8> %tmp1
    962 }
    963 
    964 define <16 x i8> @and8imm8h_lsl8(<16 x i8> %a) {
    965 ; CHECK-LABEL: and8imm8h_lsl8:
    966 ; CHECK:  bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
    967 	%tmp1 = and <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0 >
    968 	ret <16 x i8> %tmp1
    969 }
    970 
    971 define <4 x i32> @and16imm8h_lsl0(<4 x i32> %a) {
    972 ; CHECK-LABEL: and16imm8h_lsl0:
    973 ; CHECK:  bic {{v[0-9]+}}.8h, #{{0xff|255}}
    974 	%tmp1 = and <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
    975 	ret <4 x i32> %tmp1
    976 }
    977 
    978 define <4 x i32> @and16imm8h_lsl8(<4 x i32> %a) {
    979 ; CHECK-LABEL: and16imm8h_lsl8:
    980 ; CHECK:  bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
    981 	%tmp1 = and <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
    982 	ret <4 x i32> %tmp1
    983 }
    984 
    985 define <2 x i64> @and64imm8h_lsl0(<2 x i64> %a) {
    986 ; CHECK-LABEL: and64imm8h_lsl0:
    987 ; CHECK:  bic {{v[0-9]+}}.8h, #{{0xff|255}}
    988 	%tmp1 = and <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>
    989 	ret <2 x i64> %tmp1
    990 }
    991 
    992 define <2 x i64> @and64imm8h_lsl8(<2 x i64> %a) {
    993 ; CHECK-LABEL: and64imm8h_lsl8:
    994 ; CHECK:  bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
    995 	%tmp1 = and <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
    996 	ret <2 x i64> %tmp1
    997 }
    998 
    999 define <8 x i8> @orr8imm2s_lsl0(<8 x i8> %a) {
   1000 ; CHECK-LABEL: orr8imm2s_lsl0:
   1001 ; CHECK:  orr {{v[0-9]+}}.2s, #{{0xff|255}}
   1002 	%tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
   1003 	ret <8 x i8> %tmp1
   1004 }
   1005 
   1006 define <8 x i8> @orr8imm2s_lsl8(<8 x i8> %a) {
   1007 ; CHECK-LABEL: orr8imm2s_lsl8:
   1008 ; CHECK:  orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
   1009 	%tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
   1010 	ret <8 x i8> %tmp1
   1011 }
   1012 
   1013 define <8 x i8> @orr8imm2s_lsl16(<8 x i8> %a) {
   1014 ; CHECK-LABEL: orr8imm2s_lsl16:
   1015 ; CHECK:  orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
   1016 	%tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
   1017 	ret <8 x i8> %tmp1
   1018 }
   1019 
   1020 define <8 x i8> @orr8imm2s_lsl24(<8 x i8> %a) {
   1021 ; CHECK-LABEL: orr8imm2s_lsl24:
   1022 ; CHECK:  orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24
   1023 	%tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
   1024 	ret <8 x i8> %tmp1
   1025 }
   1026 
   1027 define <4 x i16> @orr16imm2s_lsl0(<4 x i16> %a) {
   1028 ; CHECK-LABEL: orr16imm2s_lsl0:
   1029 ; CHECK:  orr {{v[0-9]+}}.2s, #{{0xff|255}}
   1030 	%tmp1 = or <4 x i16> %a, < i16 255, i16 0, i16 255, i16 0>
   1031 	ret <4 x i16> %tmp1
   1032 }
   1033 
   1034 define <4 x i16> @orr16imm2s_lsl8(<4 x i16> %a) {
   1035 ; CHECK-LABEL: orr16imm2s_lsl8:
   1036 ; CHECK:  orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
   1037 	%tmp1 = or <4 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0>
   1038 	ret <4 x i16> %tmp1
   1039 }
   1040 
   1041 define <4 x i16> @orr16imm2s_lsl16(<4 x i16> %a) {
   1042 ; CHECK-LABEL: orr16imm2s_lsl16:
   1043 ; CHECK:  orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
   1044 	%tmp1 = or <4 x i16> %a, < i16 0, i16 255, i16 0, i16 255>
   1045 	ret <4 x i16> %tmp1
   1046 }
   1047 
   1048 define <4 x i16> @orr16imm2s_lsl24(<4 x i16> %a) {
   1049 ; CHECK-LABEL: orr16imm2s_lsl24:
   1050 ; CHECK:  orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24
   1051 	%tmp1 = or <4 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280>
   1052 	ret <4 x i16> %tmp1
   1053 }
   1054 
   1055 define <1 x i64> @orr64imm2s_lsl0(<1 x i64> %a) {
   1056 ; CHECK-LABEL: orr64imm2s_lsl0:
   1057 ; CHECK:  orr {{v[0-9]+}}.2s, #{{0xff|255}}
   1058 	%tmp1 = or <1 x i64> %a, < i64 1095216660735>
   1059 	ret <1 x i64> %tmp1
   1060 }
   1061 
   1062 define <1 x i64> @orr64imm2s_lsl8(<1 x i64> %a) {
   1063 ; CHECK-LABEL: orr64imm2s_lsl8:
   1064 ; CHECK:  orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
   1065 	%tmp1 = or <1 x i64> %a, < i64 280375465148160>
   1066 	ret <1 x i64> %tmp1
   1067 }
   1068 
   1069 define <1 x i64> @orr64imm2s_lsl16(<1 x i64> %a) {
   1070 ; CHECK-LABEL: orr64imm2s_lsl16:
   1071 ; CHECK:  orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
   1072 	%tmp1 = or <1 x i64> %a, < i64 71776119077928960>
   1073 	ret <1 x i64> %tmp1
   1074 }
   1075 
   1076 define <1 x i64> @orr64imm2s_lsl24(<1 x i64> %a) {
   1077 ; CHECK-LABEL: orr64imm2s_lsl24:
   1078 ; CHECK:  orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24
   1079 	%tmp1 = or <1 x i64> %a, < i64 -72057589759737856>
   1080 	ret <1 x i64> %tmp1
   1081 }
   1082 
   1083 define <16 x i8> @orr8imm4s_lsl0(<16 x i8> %a) {
   1084 ; CHECK-LABEL: orr8imm4s_lsl0:
   1085 ; CHECK:  orr {{v[0-9]+}}.4s, #{{0xff|255}}
   1086 	%tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
   1087 	ret <16 x i8> %tmp1
   1088 }
   1089 
   1090 define <16 x i8> @orr8imm4s_lsl8(<16 x i8> %a) {
   1091 ; CHECK-LABEL: orr8imm4s_lsl8:
   1092 ; CHECK:  orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
   1093 	%tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
   1094 	ret <16 x i8> %tmp1
   1095 }
   1096 
   1097 define <16 x i8> @orr8imm4s_lsl16(<16 x i8> %a) {
   1098 ; CHECK-LABEL: orr8imm4s_lsl16:
   1099 ; CHECK:  orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
   1100 	%tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
   1101 	ret <16 x i8> %tmp1
   1102 }
   1103 
   1104 define <16 x i8> @orr8imm4s_lsl24(<16 x i8> %a) {
   1105 ; CHECK-LABEL: orr8imm4s_lsl24:
   1106 ; CHECK:  orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24
   1107 	%tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
   1108 	ret <16 x i8> %tmp1
   1109 }
   1110 
   1111 define <8 x i16> @orr16imm4s_lsl0(<8 x i16> %a) {
   1112 ; CHECK-LABEL: orr16imm4s_lsl0:
   1113 ; CHECK:  orr {{v[0-9]+}}.4s, #{{0xff|255}}
   1114 	%tmp1 = or <8 x i16> %a, < i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0>
   1115 	ret <8 x i16> %tmp1
   1116 }
   1117 
   1118 define <8 x i16> @orr16imm4s_lsl8(<8 x i16> %a) {
   1119 ; CHECK-LABEL: orr16imm4s_lsl8:
   1120 ; CHECK:  orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
   1121 	%tmp1 = or <8 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0>
   1122 	ret <8 x i16> %tmp1
   1123 }
   1124 
   1125 define <8 x i16> @orr16imm4s_lsl16(<8 x i16> %a) {
   1126 ; CHECK-LABEL: orr16imm4s_lsl16:
   1127 ; CHECK:  orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
   1128 	%tmp1 = or <8 x i16> %a, < i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255>
   1129 	ret <8 x i16> %tmp1
   1130 }
   1131 
   1132 define <8 x i16> @orr16imm4s_lsl24(<8 x i16> %a) {
   1133 ; CHECK-LABEL: orr16imm4s_lsl24:
   1134 ; CHECK:  orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24
   1135 	%tmp1 = or <8 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280>
   1136 	ret <8 x i16> %tmp1
   1137 }
   1138 
   1139 define <2 x i64> @orr64imm4s_lsl0(<2 x i64> %a) {
   1140 ; CHECK-LABEL: orr64imm4s_lsl0:
   1141 ; CHECK:  orr {{v[0-9]+}}.4s, #{{0xff|255}}
   1142 	%tmp1 = or <2 x i64> %a, < i64 1095216660735, i64 1095216660735>
   1143 	ret <2 x i64> %tmp1
   1144 }
   1145 
   1146 define <2 x i64> @orr64imm4s_lsl8(<2 x i64> %a) {
   1147 ; CHECK-LABEL: orr64imm4s_lsl8:
   1148 ; CHECK:  orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
   1149 	%tmp1 = or <2 x i64> %a, < i64 280375465148160, i64 280375465148160>
   1150 	ret <2 x i64> %tmp1
   1151 }
   1152 
   1153 define <2 x i64> @orr64imm4s_lsl16(<2 x i64> %a) {
   1154 ; CHECK-LABEL: orr64imm4s_lsl16:
   1155 ; CHECK:  orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
   1156 	%tmp1 = or <2 x i64> %a, < i64 71776119077928960, i64 71776119077928960>
   1157 	ret <2 x i64> %tmp1
   1158 }
   1159 
   1160 define <2 x i64> @orr64imm4s_lsl24(<2 x i64> %a) {
   1161 ; CHECK-LABEL: orr64imm4s_lsl24:
   1162 ; CHECK:  orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24
   1163 	%tmp1 = or <2 x i64> %a, < i64 -72057589759737856, i64 -72057589759737856>
   1164 	ret <2 x i64> %tmp1
   1165 }
   1166 
   1167 define <8 x i8> @orr8imm4h_lsl0(<8 x i8> %a) {
   1168 ; CHECK-LABEL: orr8imm4h_lsl0:
   1169 ; CHECK:  orr {{v[0-9]+}}.4h, #{{0xff|255}}
   1170 	%tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
   1171 	ret <8 x i8> %tmp1
   1172 }
   1173 
   1174 define <8 x i8> @orr8imm4h_lsl8(<8 x i8> %a) {
   1175 ; CHECK-LABEL: orr8imm4h_lsl8:
   1176 ; CHECK:  orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
   1177 	%tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
   1178 	ret <8 x i8> %tmp1
   1179 }
   1180 
   1181 define <2 x i32> @orr16imm4h_lsl0(<2 x i32> %a) {
   1182 ; CHECK-LABEL: orr16imm4h_lsl0:
   1183 ; CHECK:  orr {{v[0-9]+}}.4h, #{{0xff|255}}
   1184 	%tmp1 = or <2 x i32> %a, < i32 16711935, i32 16711935>
   1185 	ret <2 x i32> %tmp1
   1186 }
   1187 
   1188 define <2 x i32> @orr16imm4h_lsl8(<2 x i32> %a) {
   1189 ; CHECK-LABEL: orr16imm4h_lsl8:
   1190 ; CHECK:  orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
   1191 	%tmp1 = or <2 x i32> %a, < i32 4278255360, i32 4278255360>
   1192 	ret <2 x i32> %tmp1
   1193 }
   1194 
   1195 define <1 x i64> @orr64imm4h_lsl0(<1 x i64> %a) {
   1196 ; CHECK-LABEL: orr64imm4h_lsl0:
   1197 ; CHECK:  orr {{v[0-9]+}}.4h, #{{0xff|255}}
   1198 	%tmp1 = or <1 x i64> %a, < i64 71777214294589695>
   1199 	ret <1 x i64> %tmp1
   1200 }
   1201 
   1202 define <1 x i64> @orr64imm4h_lsl8(<1 x i64> %a) {
   1203 ; CHECK-LABEL: orr64imm4h_lsl8:
   1204 ; CHECK:  orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
   1205 	%tmp1 = or <1 x i64> %a, < i64 -71777214294589696>
   1206 	ret <1 x i64> %tmp1
   1207 }
   1208 
   1209 define <16 x i8> @orr8imm8h_lsl0(<16 x i8> %a) {
   1210 ; CHECK-LABEL: orr8imm8h_lsl0:
   1211 ; CHECK:  orr {{v[0-9]+}}.8h, #{{0xff|255}}
   1212 	%tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
   1213 	ret <16 x i8> %tmp1
   1214 }
   1215 
   1216 define <16 x i8> @orr8imm8h_lsl8(<16 x i8> %a) {
   1217 ; CHECK-LABEL: orr8imm8h_lsl8:
   1218 ; CHECK:  orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
   1219 	%tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
   1220 	ret <16 x i8> %tmp1
   1221 }
   1222 
   1223 define <4 x i32> @orr16imm8h_lsl0(<4 x i32> %a) {
   1224 ; CHECK-LABEL: orr16imm8h_lsl0:
   1225 ; CHECK:  orr {{v[0-9]+}}.8h, #{{0xff|255}}
   1226 	%tmp1 = or <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
   1227 	ret <4 x i32> %tmp1
   1228 }
   1229 
   1230 define <4 x i32> @orr16imm8h_lsl8(<4 x i32> %a) {
   1231 ; CHECK-LABEL: orr16imm8h_lsl8:
   1232 ; CHECK:  orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
   1233 	%tmp1 = or <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
   1234 	ret <4 x i32> %tmp1
   1235 }
   1236 
   1237 define <2 x i64> @orr64imm8h_lsl0(<2 x i64> %a) {
   1238 ; CHECK-LABEL: orr64imm8h_lsl0:
   1239 ; CHECK:  orr {{v[0-9]+}}.8h, #{{0xff|255}}
   1240 	%tmp1 = or <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
   1241 	ret <2 x i64> %tmp1
   1242 }
   1243 
   1244 define <2 x i64> @orr64imm8h_lsl8(<2 x i64> %a) {
   1245 ; CHECK-LABEL: orr64imm8h_lsl8:
   1246 ; CHECK:  orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
   1247 	%tmp1 = or <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>
   1248 	ret <2 x i64> %tmp1
   1249 }
   1250 
   1251