1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s 2 3 define <8 x i16> @test_sshll_v8i8(<8 x i8> %a) { 4 ; CHECK: test_sshll_v8i8: 5 ; CHECK: sshll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #3 6 %1 = sext <8 x i8> %a to <8 x i16> 7 %tmp = shl <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> 8 ret <8 x i16> %tmp 9 } 10 11 define <4 x i32> @test_sshll_v4i16(<4 x i16> %a) { 12 ; CHECK: test_sshll_v4i16: 13 ; CHECK: sshll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #9 14 %1 = sext <4 x i16> %a to <4 x i32> 15 %tmp = shl <4 x i32> %1, <i32 9, i32 9, i32 9, i32 9> 16 ret <4 x i32> %tmp 17 } 18 19 define <2 x i64> @test_sshll_v2i32(<2 x i32> %a) { 20 ; CHECK: test_sshll_v2i32: 21 ; CHECK: sshll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #19 22 %1 = sext <2 x i32> %a to <2 x i64> 23 %tmp = shl <2 x i64> %1, <i64 19, i64 19> 24 ret <2 x i64> %tmp 25 } 26 27 define <8 x i16> @test_ushll_v8i8(<8 x i8> %a) { 28 ; CHECK: test_ushll_v8i8: 29 ; CHECK: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #3 30 %1 = zext <8 x i8> %a to <8 x i16> 31 %tmp = shl <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> 32 ret <8 x i16> %tmp 33 } 34 35 define <4 x i32> @test_ushll_v4i16(<4 x i16> %a) { 36 ; CHECK: test_ushll_v4i16: 37 ; CHECK: ushll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #9 38 %1 = zext <4 x i16> %a to <4 x i32> 39 %tmp = shl <4 x i32> %1, <i32 9, i32 9, i32 9, i32 9> 40 ret <4 x i32> %tmp 41 } 42 43 define <2 x i64> @test_ushll_v2i32(<2 x i32> %a) { 44 ; CHECK: test_ushll_v2i32: 45 ; CHECK: ushll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #19 46 %1 = zext <2 x i32> %a to <2 x i64> 47 %tmp = shl <2 x i64> %1, <i64 19, i64 19> 48 ret <2 x i64> %tmp 49 } 50 51 define <8 x i16> @test_sshll2_v16i8(<16 x i8> %a) { 52 ; CHECK: test_sshll2_v16i8: 53 ; CHECK: sshll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #3 54 %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 55 %2 = sext <8 x i8> %1 to <8 x i16> 56 %tmp = shl <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> 57 ret <8 x i16> %tmp 58 } 59 60 define <4 x i32> @test_sshll2_v8i16(<8 x i16> %a) { 61 ; CHECK: test_sshll2_v8i16: 62 ; CHECK: sshll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #9 63 %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 64 %2 = sext <4 x i16> %1 to <4 x i32> 65 %tmp = shl <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9> 66 ret <4 x i32> %tmp 67 } 68 69 define <2 x i64> @test_sshll2_v4i32(<4 x i32> %a) { 70 ; CHECK: test_sshll2_v4i32: 71 ; CHECK: sshll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #19 72 %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3> 73 %2 = sext <2 x i32> %1 to <2 x i64> 74 %tmp = shl <2 x i64> %2, <i64 19, i64 19> 75 ret <2 x i64> %tmp 76 } 77 78 define <8 x i16> @test_ushll2_v16i8(<16 x i8> %a) { 79 ; CHECK: test_ushll2_v16i8: 80 ; CHECK: ushll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #3 81 %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 82 %2 = zext <8 x i8> %1 to <8 x i16> 83 %tmp = shl <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> 84 ret <8 x i16> %tmp 85 } 86 87 define <4 x i32> @test_ushll2_v8i16(<8 x i16> %a) { 88 ; CHECK: test_ushll2_v8i16: 89 ; CHECK: ushll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #9 90 %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 91 %2 = zext <4 x i16> %1 to <4 x i32> 92 %tmp = shl <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9> 93 ret <4 x i32> %tmp 94 } 95 96 define <2 x i64> @test_ushll2_v4i32(<4 x i32> %a) { 97 ; CHECK: test_ushll2_v4i32: 98 ; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #19 99 %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3> 100 %2 = zext <2 x i32> %1 to <2 x i64> 101 %tmp = shl <2 x i64> %2, <i64 19, i64 19> 102 ret <2 x i64> %tmp 103 } 104 105 define <8 x i16> @test_sshll_shl0_v8i8(<8 x i8> %a) { 106 ; CHECK: test_sshll_shl0_v8i8: 107 ; CHECK: sshll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0 108 %tmp = sext <8 x i8> %a to <8 x i16> 109 ret <8 x i16> %tmp 110 } 111 112 define <4 x i32> @test_sshll_shl0_v4i16(<4 x i16> %a) { 113 ; CHECK: test_sshll_shl0_v4i16: 114 ; CHECK: sshll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #0 115 %tmp = sext <4 x i16> %a to <4 x i32> 116 ret <4 x i32> %tmp 117 } 118 119 define <2 x i64> @test_sshll_shl0_v2i32(<2 x i32> %a) { 120 ; CHECK: test_sshll_shl0_v2i32: 121 ; CHECK: sshll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #0 122 %tmp = sext <2 x i32> %a to <2 x i64> 123 ret <2 x i64> %tmp 124 } 125 126 define <8 x i16> @test_ushll_shl0_v8i8(<8 x i8> %a) { 127 ; CHECK: test_ushll_shl0_v8i8: 128 ; CHECK: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0 129 %tmp = zext <8 x i8> %a to <8 x i16> 130 ret <8 x i16> %tmp 131 } 132 133 define <4 x i32> @test_ushll_shl0_v4i16(<4 x i16> %a) { 134 ; CHECK: test_ushll_shl0_v4i16: 135 ; CHECK: ushll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #0 136 %tmp = zext <4 x i16> %a to <4 x i32> 137 ret <4 x i32> %tmp 138 } 139 140 define <2 x i64> @test_ushll_shl0_v2i32(<2 x i32> %a) { 141 ; CHECK: test_ushll_shl0_v2i32: 142 ; CHECK: ushll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #0 143 %tmp = zext <2 x i32> %a to <2 x i64> 144 ret <2 x i64> %tmp 145 } 146 147 define <8 x i16> @test_sshll2_shl0_v16i8(<16 x i8> %a) { 148 ; CHECK: test_sshll2_shl0_v16i8: 149 ; CHECK: sshll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #0 150 %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 151 %tmp = sext <8 x i8> %1 to <8 x i16> 152 ret <8 x i16> %tmp 153 } 154 155 define <4 x i32> @test_sshll2_shl0_v8i16(<8 x i16> %a) { 156 ; CHECK: test_sshll2_shl0_v8i16: 157 ; CHECK: sshll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #0 158 %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 159 %tmp = sext <4 x i16> %1 to <4 x i32> 160 ret <4 x i32> %tmp 161 } 162 163 define <2 x i64> @test_sshll2_shl0_v4i32(<4 x i32> %a) { 164 ; CHECK: test_sshll2_shl0_v4i32: 165 ; CHECK: sshll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #0 166 %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3> 167 %tmp = sext <2 x i32> %1 to <2 x i64> 168 ret <2 x i64> %tmp 169 } 170 171 define <8 x i16> @test_ushll2_shl0_v16i8(<16 x i8> %a) { 172 ; CHECK: test_ushll2_shl0_v16i8: 173 ; CHECK: ushll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #0 174 %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 175 %tmp = zext <8 x i8> %1 to <8 x i16> 176 ret <8 x i16> %tmp 177 } 178 179 define <4 x i32> @test_ushll2_shl0_v8i16(<8 x i16> %a) { 180 ; CHECK: test_ushll2_shl0_v8i16: 181 ; CHECK: ushll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #0 182 %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 183 %tmp = zext <4 x i16> %1 to <4 x i32> 184 ret <4 x i32> %tmp 185 } 186 187 define <2 x i64> @test_ushll2_shl0_v4i32(<4 x i32> %a) { 188 ; CHECK: test_ushll2_shl0_v4i32: 189 ; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #0 190 %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3> 191 %tmp = zext <2 x i32> %1 to <2 x i64> 192 ret <2 x i64> %tmp 193 } 194 195 define <8 x i16> @test_ushll_cmp(<8 x i8> %a, <8 x i8> %b) #0 { 196 ; CHECK: test_ushll_cmp: 197 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 198 ; CHECK-NEXT: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0 199 %cmp.i = icmp eq <8 x i8> %a, %b 200 %vcgtz.i.i = sext <8 x i1> %cmp.i to <8 x i8> 201 %vmovl.i.i.i = zext <8 x i8> %vcgtz.i.i to <8 x i16> 202 ret <8 x i16> %vmovl.i.i.i 203 } 204
