1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK %s 3 4 ; CHECK-LABEL: {{^}}test1: 5 ; CHECK: image_store 6 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0){{$}} 7 ; CHECK-NEXT: image_store 8 ; CHECK-NEXT: s_endpgm 9 define amdgpu_ps void @test1(<8 x i32> inreg %rsrc, <4 x float> %d0, <4 x float> %d1, i32 %c0, i32 %c1) { 10 call void @llvm.amdgcn.image.store.i32(<4 x float> %d0, i32 %c0, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 1, i1 0) 11 call void @llvm.amdgcn.s.waitcnt(i32 3840) ; 0xf00 12 call void @llvm.amdgcn.image.store.i32(<4 x float> %d1, i32 %c1, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 1, i1 0) 13 ret void 14 } 15 16 ; Test that the intrinsic is merged with automatically generated waits and 17 ; emitted as late as possible. 18 ; 19 ; CHECK-LABEL: {{^}}test2: 20 ; CHECK: image_load 21 ; CHECK-NOT: s_waitcnt vmcnt(0){{$}} 22 ; CHECK: s_waitcnt 23 ; CHECK-NEXT: image_store 24 define amdgpu_ps void @test2(<8 x i32> inreg %rsrc, i32 %c) { 25 %t = call <4 x float> @llvm.amdgcn.image.load.i32(i32 %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) 26 call void @llvm.amdgcn.s.waitcnt(i32 3840) ; 0xf00 27 %c.1 = mul i32 %c, 2 28 call void @llvm.amdgcn.image.store.i32(<4 x float> %t, i32 %c.1, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) 29 ret void 30 } 31 32 declare void @llvm.amdgcn.s.waitcnt(i32) #0 33 34 declare <4 x float> @llvm.amdgcn.image.load.i32(i32, <8 x i32>, i32, i1, i1, i1, i1) #1 35 declare void @llvm.amdgcn.image.store.i32(<4 x float>, i32, <8 x i32>, i32, i1, i1, i1, i1) #0 36 37 attributes #0 = { nounwind } 38 attributes #1 = { nounwind readonly } 39
