1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 2 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s 3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 4 5 @local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4 6 7 8 ; Check that the LDS size emitted correctly 9 ; EG: .long 166120 10 ; EG-NEXT: .long 128 11 ; SI: .long 47180 12 ; SI-NEXT: .long 65668 13 ; CI: .long 47180 14 ; CI-NEXT: .long 32900 15 16 ; FUNC-LABEL: {{^}}local_memory: 17 18 ; EG: LDS_WRITE 19 ; SI-NOT: s_wqm_b64 20 ; SI: ds_write_b32 21 22 ; GROUP_BARRIER must be the last instruction in a clause 23 ; EG: GROUP_BARRIER 24 ; EG-NEXT: ALU clause 25 ; SI: s_barrier 26 27 ; EG: LDS_READ_RET 28 ; SI: ds_read_b32 {{v[0-9]+}}, 29 30 define void @local_memory(i32 addrspace(1)* %out) { 31 entry: 32 %y.i = call i32 @llvm.r600.read.tidig.x() #0 33 %arrayidx = getelementptr inbounds [128 x i32], [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %y.i 34 store i32 %y.i, i32 addrspace(3)* %arrayidx, align 4 35 %add = add nsw i32 %y.i, 1 36 %cmp = icmp eq i32 %add, 16 37 %.add = select i1 %cmp, i32 0, i32 %add 38 call void @llvm.AMDGPU.barrier.local() 39 %arrayidx1 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %.add 40 %0 = load i32, i32 addrspace(3)* %arrayidx1, align 4 41 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %y.i 42 store i32 %0, i32 addrspace(1)* %arrayidx2, align 4 43 ret void 44 } 45 46 @lds = addrspace(3) global [512 x i32] undef, align 4 47 48 ; On SI we need to make sure that the base offset is a register and not 49 ; an immediate. 50 ; FUNC-LABEL: {{^}}load_i32_local_const_ptr: 51 ; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0 52 ; GCN: ds_read_b32 v{{[0-9]+}}, v[[ZERO]] offset:4 53 ; R600: LDS_READ_RET 54 define void @load_i32_local_const_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { 55 entry: 56 %tmp0 = getelementptr [512 x i32], [512 x i32] addrspace(3)* @lds, i32 0, i32 1 57 %tmp1 = load i32, i32 addrspace(3)* %tmp0 58 %tmp2 = getelementptr i32, i32 addrspace(1)* %out, i32 1 59 store i32 %tmp1, i32 addrspace(1)* %tmp2 60 ret void 61 } 62 63 ; Test loading a i32 and v2i32 value from the same base pointer. 64 ; FUNC-LABEL: {{^}}load_i32_v2i32_local: 65 ; R600: LDS_READ_RET 66 ; R600: LDS_READ_RET 67 ; R600: LDS_READ_RET 68 ; GCN-DAG: ds_read_b32 69 ; GCN-DAG: ds_read2_b32 70 define void @load_i32_v2i32_local(<2 x i32> addrspace(1)* %out, i32 addrspace(3)* %in) { 71 %scalar = load i32, i32 addrspace(3)* %in 72 %tmp0 = bitcast i32 addrspace(3)* %in to <2 x i32> addrspace(3)* 73 %vec_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(3)* %tmp0, i32 2 74 %vec0 = load <2 x i32>, <2 x i32> addrspace(3)* %vec_ptr, align 4 75 %vec1 = insertelement <2 x i32> <i32 0, i32 0>, i32 %scalar, i32 0 76 %vec = add <2 x i32> %vec0, %vec1 77 store <2 x i32> %vec, <2 x i32> addrspace(1)* %out 78 ret void 79 } 80 81 declare i32 @llvm.r600.read.tidig.x() #0 82 declare void @llvm.AMDGPU.barrier.local() 83 84 attributes #0 = { readnone } 85
