1 ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rv710 | FileCheck %s 2 3 ; CHECK: TEX 9 @6 ; encoding: [0x06,0x00,0x00,0x00,0x00,0x04,0x88,0x80] 4 define amdgpu_vs void @test(<4 x float> inreg %reg0, <4 x float> inreg %reg1) { 5 bb: 6 %tmp = extractelement <4 x float> %reg1, i32 0 7 %tmp1 = extractelement <4 x float> %reg1, i32 1 8 %tmp2 = extractelement <4 x float> %reg1, i32 2 9 %tmp3 = extractelement <4 x float> %reg1, i32 3 10 %tmp4 = insertelement <4 x float> undef, float %tmp, i32 0 11 %tmp5 = insertelement <4 x float> %tmp4, float %tmp1, i32 1 12 %tmp6 = insertelement <4 x float> %tmp5, float %tmp2, i32 2 13 %tmp7 = insertelement <4 x float> %tmp6, float %tmp3, i32 3 14 %tmp8 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 15 %tmp9 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) 16 %tmp10 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 17 %tmp11 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp10, i32 0, i32 0, i32 0, i32 1, i32 0, i32 1, i32 1, i32 1, i32 1) 18 %tmp12 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 19 %tmp13 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp12, i32 0, i32 0, i32 0, i32 2, i32 0, i32 1, i32 1, i32 1, i32 1) 20 %tmp14 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 21 %tmp15 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp14, i32 0, i32 0, i32 0, i32 3, i32 0, i32 1, i32 1, i32 1, i32 1) 22 %tmp16 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 23 %tmp17 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp16, i32 0, i32 0, i32 0, i32 4, i32 0, i32 1, i32 1, i32 1, i32 1) 24 %tmp18 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 25 %tmp19 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp18, i32 0, i32 0, i32 0, i32 5, i32 0, i32 1, i32 1, i32 1, i32 1) 26 %tmp20 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 27 %tmp21 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp20, i32 0, i32 0, i32 0, i32 6, i32 0, i32 1, i32 1, i32 1, i32 1) 28 %tmp22 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 29 %tmp23 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp22, i32 0, i32 0, i32 0, i32 7, i32 0, i32 1, i32 1, i32 1, i32 1) 30 %tmp24 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 31 %tmp25 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp24, i32 0, i32 0, i32 0, i32 8, i32 0, i32 1, i32 1, i32 1, i32 1) 32 %tmp26 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 33 %tmp27 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp26, i32 0, i32 0, i32 0, i32 9, i32 0, i32 1, i32 1, i32 1, i32 1) 34 %tmp28 = fadd <4 x float> %tmp9, %tmp11 35 %tmp29 = fadd <4 x float> %tmp28, %tmp13 36 %tmp30 = fadd <4 x float> %tmp29, %tmp15 37 %tmp31 = fadd <4 x float> %tmp30, %tmp17 38 %tmp32 = fadd <4 x float> %tmp31, %tmp19 39 %tmp33 = fadd <4 x float> %tmp32, %tmp21 40 %tmp34 = fadd <4 x float> %tmp33, %tmp23 41 %tmp35 = fadd <4 x float> %tmp34, %tmp25 42 %tmp36 = fadd <4 x float> %tmp35, %tmp27 43 call void @llvm.R600.store.swizzle(<4 x float> %tmp36, i32 0, i32 2) 44 ret void 45 } 46 47 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) 48 49 ; Function Attrs: nounwind readnone 50 declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #0 51 52 attributes #0 = { nounwind readnone } 53
