1 ; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=SI %s 2 ; XUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=VI %s 3 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s 4 5 declare i32 @llvm.r600.read.tidig.x() #0 6 7 8 ;EG: {{^}}shl_v2i32: 9 ;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 10 ;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 11 12 ;SI: {{^}}shl_v2i32: 13 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 14 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 15 16 ;VI: {{^}}shl_v2i32: 17 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 18 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 19 20 define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { 21 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 22 %a = load <2 x i32>, <2 x i32> addrspace(1) * %in 23 %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr 24 %result = shl <2 x i32> %a, %b 25 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 26 ret void 27 } 28 29 ;EG: {{^}}shl_v4i32: 30 ;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 31 ;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 32 ;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 33 ;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 34 35 ;SI: {{^}}shl_v4i32: 36 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 37 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 38 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 39 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 40 41 ;VI: {{^}}shl_v4i32: 42 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 43 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 44 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 45 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 46 47 define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { 48 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1 49 %a = load <4 x i32>, <4 x i32> addrspace(1) * %in 50 %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr 51 %result = shl <4 x i32> %a, %b 52 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 53 ret void 54 } 55 56 ;EG-LABEL: {{^}}shl_i64: 57 ;EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]] 58 ;EG: LSHR {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}} 59 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal 60 ;EG-DAG: LSHR {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1 61 ;EG-DAG: LSHL {{\*? *}}[[HISMTMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], [[SHIFT]] 62 ;EG-DAG: OR_INT {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], {{[[HISMTMP]]|PV.[XYZW]|PS}}, {{[[OVERF]]|PV.[XYZW]}} 63 ;EG-DAG: LSHL {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], [[OPLO]], {{PS|[[SHIFT]]|PV.[XYZW]}} 64 ;EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal 65 ;EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} 66 ;EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0 67 68 ;SI: {{^}}shl_i64: 69 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 70 71 ;VI: {{^}}shl_i64: 72 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 73 74 define void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 75 %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1 76 %a = load i64, i64 addrspace(1) * %in 77 %b = load i64, i64 addrspace(1) * %b_ptr 78 %result = shl i64 %a, %b 79 store i64 %result, i64 addrspace(1)* %out 80 ret void 81 } 82 83 ;EG-LABEL: {{^}}shl_v2i64: 84 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] 85 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] 86 ;EG-DAG: LSHR {{\*? *}}[[COMPSHA]] 87 ;EG-DAG: LSHR {{\*? *}}[[COMPSHB]] 88 ;EG-DAG: LSHR {{.*}}, 1 89 ;EG-DAG: LSHR {{.*}}, 1 90 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal 91 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal 92 ;EG-DAG: LSHL {{.*}}, [[SHA]] 93 ;EG-DAG: LSHL {{.*}}, [[SHB]] 94 ;EG-DAG: LSHL {{.*}}, [[SHA]] 95 ;EG-DAG: LSHL {{.*}}, [[SHB]] 96 ;EG-DAG: LSHL 97 ;EG-DAG: LSHL 98 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal 99 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal 100 ;EG-DAG: CNDE_INT {{.*}}, 0.0 101 ;EG-DAG: CNDE_INT {{.*}}, 0.0 102 ;EG-DAG: CNDE_INT 103 ;EG-DAG: CNDE_INT 104 105 ;SI: {{^}}shl_v2i64: 106 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 107 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 108 109 ;VI: {{^}}shl_v2i64: 110 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 111 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 112 113 define void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { 114 %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1 115 %a = load <2 x i64>, <2 x i64> addrspace(1) * %in 116 %b = load <2 x i64>, <2 x i64> addrspace(1) * %b_ptr 117 %result = shl <2 x i64> %a, %b 118 store <2 x i64> %result, <2 x i64> addrspace(1)* %out 119 ret void 120 } 121 122 ;EG: {{^}}shl_v4i64: 123 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] 124 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] 125 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]] 126 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]] 127 ;EG-DAG: LSHR {{\*? *}}[[COMPSHA]] 128 ;EG-DAG: LSHR {{\*? *}}[[COMPSHB]] 129 ;EG-DAG: LSHR {{\*? *}}[[COMPSHC]] 130 ;EG-DAG: LSHR {{\*? *}}[[COMPSHD]] 131 ;EG-DAG: LSHR {{.*}}, 1 132 ;EG-DAG: LSHR {{.*}}, 1 133 ;EG-DAG: LSHR {{.*}}, 1 134 ;EG-DAG: LSHR {{.*}}, 1 135 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal 136 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal 137 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal 138 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal 139 ;EG-DAG: LSHL {{.*}}, [[SHA]] 140 ;EG-DAG: LSHL {{.*}}, [[SHB]] 141 ;EG-DAG: LSHL {{.*}}, [[SHC]] 142 ;EG-DAG: LSHL {{.*}}, [[SHD]] 143 ;EG-DAG: LSHL {{.*}}, [[SHA]] 144 ;EG-DAG: LSHL {{.*}}, [[SHB]] 145 ;EG-DAG: LSHL {{.*}}, [[SHC]] 146 ;EG-DAG: LSHL {{.*}}, [[SHD]] 147 ;EG-DAG: LSHL 148 ;EG-DAG: LSHL 149 ;EG-DAG: LSHL 150 ;EG-DAG: LSHL 151 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal 152 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal 153 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal 154 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal 155 ;EG-DAG: CNDE_INT {{.*}}, 0.0 156 ;EG-DAG: CNDE_INT {{.*}}, 0.0 157 ;EG-DAG: CNDE_INT {{.*}}, 0.0 158 ;EG-DAG: CNDE_INT {{.*}}, 0.0 159 ;EG-DAG: CNDE_INT 160 ;EG-DAG: CNDE_INT 161 ;EG-DAG: CNDE_INT 162 ;EG-DAG: CNDE_INT 163 164 ;SI: {{^}}shl_v4i64: 165 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 166 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 167 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 168 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 169 170 ;VI: {{^}}shl_v4i64: 171 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 172 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 173 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 174 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 175 176 define void @shl_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { 177 %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1 178 %a = load <4 x i64>, <4 x i64> addrspace(1) * %in 179 %b = load <4 x i64>, <4 x i64> addrspace(1) * %b_ptr 180 %result = shl <4 x i64> %a, %b 181 store <4 x i64> %result, <4 x i64> addrspace(1)* %out 182 ret void 183 } 184 185 ; Make sure load width gets reduced to i32 load. 186 ; GCN-LABEL: {{^}}s_shl_32_i64: 187 ; GCN-DAG: s_load_dword [[LO_A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb{{$}} 188 ; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], 0{{$}} 189 ; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[LO_A]] 190 ; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} 191 define void @s_shl_32_i64(i64 addrspace(1)* %out, i64 %a) { 192 %result = shl i64 %a, 32 193 store i64 %result, i64 addrspace(1)* %out 194 ret void 195 } 196 197 ; GCN-LABEL: {{^}}v_shl_32_i64: 198 ; GCN-DAG: buffer_load_dword v[[LO_A:[0-9]+]], 199 ; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], 0{{$}} 200 ; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[LO_A]]{{\]}} 201 define void @v_shl_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 202 %tid = call i32 @llvm.r600.read.tidig.x() #0 203 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 204 %gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 205 %a = load i64, i64 addrspace(1)* %gep.in 206 %result = shl i64 %a, 32 207 store i64 %result, i64 addrspace(1)* %gep.out 208 ret void 209 } 210 211 ; FUNC-LABEL: {{^}}s_shl_constant_i64 212 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 213 define void @s_shl_constant_i64(i64 addrspace(1)* %out, i64 %a) { 214 %shl = shl i64 281474976710655, %a 215 store i64 %shl, i64 addrspace(1)* %out, align 8 216 ret void 217 } 218 219 ; FUNC-LABEL: {{^}}v_shl_constant_i64: 220 ; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]] 221 ; SI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0xab19b207 222 ; SI-DAG: s_movk_i32 s[[KHI:[0-9]+]], 0x11e{{$}} 223 ; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}, [[VAL]] 224 ; SI: buffer_store_dwordx2 225 define void @v_shl_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 226 %a = load i64, i64 addrspace(1)* %aptr, align 8 227 %shl = shl i64 1231231234567, %a 228 store i64 %shl, i64 addrspace(1)* %out, align 8 229 ret void 230 } 231 232 ; FUNC-LABEL: {{^}}v_shl_i64_32_bit_constant: 233 ; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]] 234 ; SI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0x12d687{{$}} 235 ; SI-DAG: s_mov_b32 s[[KHI:[0-9]+]], 0{{$}} 236 ; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}, [[VAL]] 237 define void @v_shl_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 238 %a = load i64, i64 addrspace(1)* %aptr, align 8 239 %shl = shl i64 1234567, %a 240 store i64 %shl, i64 addrspace(1)* %out, align 8 241 ret void 242 } 243 244 ; FUNC-LABEL: {{^}}v_shl_inline_imm_64_i64: 245 ; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, 64, {{v[0-9]+}} 246 define void @v_shl_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 247 %a = load i64, i64 addrspace(1)* %aptr, align 8 248 %shl = shl i64 64, %a 249 store i64 %shl, i64 addrspace(1)* %out, align 8 250 ret void 251 } 252 253 ; FUNC-LABEL: {{^}}s_shl_inline_imm_64_i64: 254 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 64, s{{[0-9]+}} 255 define void @s_shl_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 256 %shl = shl i64 64, %a 257 store i64 %shl, i64 addrspace(1)* %out, align 8 258 ret void 259 } 260 261 ; FUNC-LABEL: {{^}}s_shl_inline_imm_1_i64: 262 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 1, s{{[0-9]+}} 263 define void @s_shl_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 264 %shl = shl i64 1, %a 265 store i64 %shl, i64 addrspace(1)* %out, align 8 266 ret void 267 } 268 269 ; FUNC-LABEL: {{^}}s_shl_inline_imm_1.0_i64: 270 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, s{{[0-9]+}} 271 define void @s_shl_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 272 %shl = shl i64 4607182418800017408, %a 273 store i64 %shl, i64 addrspace(1)* %out, align 8 274 ret void 275 } 276 277 ; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_1.0_i64: 278 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -1.0, s{{[0-9]+}} 279 define void @s_shl_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 280 %shl = shl i64 13830554455654793216, %a 281 store i64 %shl, i64 addrspace(1)* %out, align 8 282 ret void 283 } 284 285 ; FUNC-LABEL: {{^}}s_shl_inline_imm_0.5_i64: 286 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 0.5, s{{[0-9]+}} 287 define void @s_shl_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 288 %shl = shl i64 4602678819172646912, %a 289 store i64 %shl, i64 addrspace(1)* %out, align 8 290 ret void 291 } 292 293 ; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_0.5_i64: 294 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -0.5, s{{[0-9]+}} 295 define void @s_shl_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 296 %shl = shl i64 13826050856027422720, %a 297 store i64 %shl, i64 addrspace(1)* %out, align 8 298 ret void 299 } 300 301 ; FUNC-LABEL: {{^}}s_shl_inline_imm_2.0_i64: 302 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 2.0, s{{[0-9]+}} 303 define void @s_shl_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 304 %shl = shl i64 4611686018427387904, %a 305 store i64 %shl, i64 addrspace(1)* %out, align 8 306 ret void 307 } 308 309 ; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_2.0_i64: 310 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -2.0, s{{[0-9]+}} 311 define void @s_shl_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 312 %shl = shl i64 13835058055282163712, %a 313 store i64 %shl, i64 addrspace(1)* %out, align 8 314 ret void 315 } 316 317 ; FUNC-LABEL: {{^}}s_shl_inline_imm_4.0_i64: 318 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 4.0, s{{[0-9]+}} 319 define void @s_shl_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 320 %shl = shl i64 4616189618054758400, %a 321 store i64 %shl, i64 addrspace(1)* %out, align 8 322 ret void 323 } 324 325 ; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_4.0_i64: 326 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -4.0, s{{[0-9]+}} 327 define void @s_shl_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 328 %shl = shl i64 13839561654909534208, %a 329 store i64 %shl, i64 addrspace(1)* %out, align 8 330 ret void 331 } 332 333 334 ; Test with the 64-bit integer bitpattern for a 32-bit float in the 335 ; low 32-bits, which is not a valid 64-bit inline immmediate. 336 337 ; FUNC-LABEL: {{^}}s_shl_inline_imm_f32_4.0_i64: 338 ; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 4.0 339 ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0{{$}} 340 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, s{{[0-9]+}} 341 define void @s_shl_inline_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 342 %shl = shl i64 1082130432, %a 343 store i64 %shl, i64 addrspace(1)* %out, align 8 344 ret void 345 } 346 347 ; FIXME: Copy of -1 register 348 ; FUNC-LABEL: {{^}}s_shl_inline_imm_f32_neg_4.0_i64: 349 ; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], -4.0 350 ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -1{{$}} 351 ; SI-DAG: s_mov_b32 s[[K_HI_COPY:[0-9]+]], s[[K_HI]] 352 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI_COPY]]{{\]}}, s{{[0-9]+}} 353 define void @s_shl_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 354 %shl = shl i64 -1065353216, %a 355 store i64 %shl, i64 addrspace(1)* %out, align 8 356 ret void 357 } 358 359 ; Shift into upper 32-bits 360 ; FUNC-LABEL: {{^}}s_shl_inline_high_imm_f32_4.0_i64: 361 ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 4.0 362 ; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}} 363 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, s{{[0-9]+}} 364 define void @s_shl_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 365 %shl = shl i64 4647714815446351872, %a 366 store i64 %shl, i64 addrspace(1)* %out, align 8 367 ret void 368 } 369 370 ; FUNC-LABEL: {{^}}s_shl_inline_high_imm_f32_neg_4.0_i64: 371 ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -4.0 372 ; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}} 373 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, s{{[0-9]+}} 374 define void @s_shl_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 375 %shl = shl i64 13871086852301127680, %a 376 store i64 %shl, i64 addrspace(1)* %out, align 8 377 ret void 378 } 379 380 attributes #0 = { nounwind readnone } 381
