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      1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
      2 
      3 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
      4 
      5 ; SI-LABEL: {{^}}sint_to_fp_i32_to_f64
      6 ; SI: v_cvt_f64_i32_e32
      7 define void @sint_to_fp_i32_to_f64(double addrspace(1)* %out, i32 %in) {
      8   %result = sitofp i32 %in to double
      9   store double %result, double addrspace(1)* %out
     10   ret void
     11 }
     12 
     13 ; We can't fold the SGPRs into v_cndmask_b32_e64, because it already
     14 ; uses an SGPR (implicit vcc).
     15 
     16 ; SI-LABEL: {{^}}sint_to_fp_i1_f64:
     17 ; SI-DAG: v_cmp_eq_i32_e64 vcc,
     18 ; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}}
     19 ; SI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
     20 ; SI: buffer_store_dwordx2 v{{\[}}[[ZERO]]:[[SEL]]{{\]}}
     21 ; SI: s_endpgm
     22 define void @sint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) {
     23   %cmp = icmp eq i32 %in, 0
     24   %fp = sitofp i1 %cmp to double
     25   store double %fp, double addrspace(1)* %out, align 4
     26   ret void
     27 }
     28 
     29 ; SI-LABEL: {{^}}sint_to_fp_i1_f64_load:
     30 ; SI: v_cndmask_b32_e64 [[IRESULT:v[0-9]]], 0, -1
     31 ; SI-NEXT: v_cvt_f64_i32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]]
     32 ; SI: buffer_store_dwordx2 [[RESULT]]
     33 ; SI: s_endpgm
     34 define void @sint_to_fp_i1_f64_load(double addrspace(1)* %out, i1 %in) {
     35   %fp = sitofp i1 %in to double
     36   store double %fp, double addrspace(1)* %out, align 8
     37   ret void
     38 }
     39 
     40 ; SI-LABEL: @s_sint_to_fp_i64_to_f64
     41 define void @s_sint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 %in) {
     42   %result = sitofp i64 %in to double
     43   store double %result, double addrspace(1)* %out
     44   ret void
     45 }
     46 
     47 ; SI-LABEL: @v_sint_to_fp_i64_to_f64
     48 ; SI: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
     49 ; SI-DAG: v_cvt_f64_i32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]]
     50 ; SI-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]]
     51 ; SI-DAG: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32
     52 ; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]]
     53 ; SI: buffer_store_dwordx2 [[RESULT]]
     54 define void @v_sint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) {
     55   %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
     56   %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
     57   %val = load i64, i64 addrspace(1)* %gep, align 8
     58   %result = sitofp i64 %val to double
     59   store double %result, double addrspace(1)* %out
     60   ret void
     61 }
     62