1 ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6,+vfp2 | FileCheck %s 2 ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6,+vfp2 | FileCheck --check-prefix=DOMAIN %s 3 4 ; The execution domain checking code would translate vmovs to vorr whether or not 5 ; we had NEON instructions. Verify we don't if we're not compiled with NEON. 6 ; DOMAIN-NOT: vorr 7 @quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] 8 @dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] 9 @A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1] 10 11 ; CHECK-LABEL: dct_luma_sp: 12 define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) { 13 entry: 14 ; Make sure to use base-updating stores for saving callee-saved registers. 15 ; CHECK: push 16 ; CHECK-NOT: sub sp 17 ; CHECK: push 18 %predicted_block = alloca [4 x [4 x i32]], align 4 ; <[4 x [4 x i32]]*> [#uses=1] 19 br label %cond_next489 20 21 cond_next489: ; preds = %cond_false, %bb471 22 %j.7.in = load i8, i8* null ; <i8> [#uses=1] 23 %i.8.in = load i8, i8* null ; <i8> [#uses=1] 24 %i.8 = zext i8 %i.8.in to i32 ; <i32> [#uses=4] 25 %j.7 = zext i8 %j.7.in to i32 ; <i32> [#uses=4] 26 %tmp495 = getelementptr [4 x [4 x i32]], [4 x [4 x i32]]* %predicted_block, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=2] 27 %tmp496 = load i32, i32* %tmp495 ; <i32> [#uses=2] 28 %tmp502 = load i32, i32* null ; <i32> [#uses=1] 29 %tmp542 = getelementptr [6 x [4 x [4 x i32]]], [6 x [4 x [4 x i32]]]* @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1] 30 %tmp543 = load i32, i32* %tmp542 ; <i32> [#uses=1] 31 %tmp548 = ashr i32 0, 0 ; <i32> [#uses=3] 32 %tmp561 = sub i32 0, %tmp496 ; <i32> [#uses=3] 33 %abscond563 = icmp sgt i32 %tmp561, -1 ; <i1> [#uses=1] 34 %abs564 = select i1 %abscond563, i32 %tmp561, i32 0 ; <i32> [#uses=1] 35 %tmp572 = mul i32 %abs564, %tmp543 ; <i32> [#uses=1] 36 %tmp574 = add i32 %tmp572, 0 ; <i32> [#uses=1] 37 %tmp576 = ashr i32 %tmp574, 0 ; <i32> [#uses=7] 38 %tmp579 = icmp eq i32 %tmp548, %tmp576 ; <i1> [#uses=1] 39 br i1 %tmp579, label %bb712, label %cond_next589 40 41 cond_next589: ; preds = %cond_next489 42 %tmp605 = getelementptr [6 x [4 x [4 x i32]]], [6 x [4 x [4 x i32]]]* @dequant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1] 43 %tmp606 = load i32, i32* %tmp605 ; <i32> [#uses=1] 44 %tmp612 = load i32, i32* null ; <i32> [#uses=1] 45 %tmp629 = load i32, i32* null ; <i32> [#uses=1] 46 %tmp629a = sitofp i32 %tmp629 to double ; <double> [#uses=1] 47 %tmp631 = fmul double %tmp629a, 0.000000e+00 ; <double> [#uses=1] 48 %tmp632 = fadd double 0.000000e+00, %tmp631 ; <double> [#uses=1] 49 %tmp642 = call fastcc i32 @sign( i32 %tmp576, i32 %tmp561 ) ; <i32> [#uses=1] 50 %tmp650 = mul i32 %tmp606, %tmp642 ; <i32> [#uses=1] 51 %tmp656 = mul i32 %tmp650, %tmp612 ; <i32> [#uses=1] 52 %tmp658 = shl i32 %tmp656, 0 ; <i32> [#uses=1] 53 %tmp659 = ashr i32 %tmp658, 6 ; <i32> [#uses=1] 54 %tmp660 = sub i32 0, %tmp659 ; <i32> [#uses=1] 55 %tmp666 = sub i32 %tmp660, %tmp496 ; <i32> [#uses=1] 56 %tmp667 = sitofp i32 %tmp666 to double ; <double> [#uses=2] 57 call void @levrun_linfo_inter( i32 %tmp576, i32 0, i32* null, i32* null ) 58 %tmp671 = fmul double %tmp667, %tmp667 ; <double> [#uses=1] 59 %tmp675 = fadd double %tmp671, 0.000000e+00 ; <double> [#uses=1] 60 %tmp678 = fcmp oeq double %tmp632, %tmp675 ; <i1> [#uses=1] 61 br i1 %tmp678, label %cond_true679, label %cond_false693 62 63 cond_true679: ; preds = %cond_next589 64 %abscond681 = icmp sgt i32 %tmp548, -1 ; <i1> [#uses=1] 65 %abs682 = select i1 %abscond681, i32 %tmp548, i32 0 ; <i32> [#uses=1] 66 %abscond684 = icmp sgt i32 %tmp576, -1 ; <i1> [#uses=1] 67 %abs685 = select i1 %abscond684, i32 %tmp576, i32 0 ; <i32> [#uses=1] 68 %tmp686 = icmp slt i32 %abs682, %abs685 ; <i1> [#uses=1] 69 br i1 %tmp686, label %cond_next702, label %cond_false689 70 71 cond_false689: ; preds = %cond_true679 72 %tmp739 = icmp eq i32 %tmp576, 0 ; <i1> [#uses=1] 73 br i1 %tmp579, label %bb737, label %cond_false708 74 75 cond_false693: ; preds = %cond_next589 76 ret i32 0 77 78 cond_next702: ; preds = %cond_true679 79 ret i32 0 80 81 cond_false708: ; preds = %cond_false689 82 ret i32 0 83 84 bb712: ; preds = %cond_next489 85 ret i32 0 86 87 bb737: ; preds = %cond_false689 88 br i1 %tmp739, label %cond_next791, label %cond_true740 89 90 cond_true740: ; preds = %bb737 91 %tmp761 = call fastcc i32 @sign( i32 %tmp576, i32 0 ) ; <i32> [#uses=1] 92 %tmp780 = load i32, i32* null ; <i32> [#uses=1] 93 %tmp785 = getelementptr [4 x [4 x i32]], [4 x [4 x i32]]* @A, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1] 94 %tmp786 = load i32, i32* %tmp785 ; <i32> [#uses=1] 95 %tmp781 = mul i32 %tmp780, %tmp761 ; <i32> [#uses=1] 96 %tmp787 = mul i32 %tmp781, %tmp786 ; <i32> [#uses=1] 97 %tmp789 = shl i32 %tmp787, 0 ; <i32> [#uses=1] 98 %tmp790 = ashr i32 %tmp789, 6 ; <i32> [#uses=1] 99 br label %cond_next791 100 101 cond_next791: ; preds = %cond_true740, %bb737 102 %ilev.1 = phi i32 [ %tmp790, %cond_true740 ], [ 0, %bb737 ] ; <i32> [#uses=1] 103 %tmp796 = load i32, i32* %tmp495 ; <i32> [#uses=1] 104 %tmp798 = add i32 %tmp796, %ilev.1 ; <i32> [#uses=1] 105 %tmp812 = mul i32 0, %tmp502 ; <i32> [#uses=0] 106 %tmp818 = call fastcc i32 @sign( i32 0, i32 %tmp798 ) ; <i32> [#uses=0] 107 unreachable 108 } 109 110 declare i32 @sign(i32, i32) 111 112 declare void @levrun_linfo_inter(i32, i32, i32*, i32*) 113
