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      1 ; RUN: llc < %s -asm-verbose=false -O3  -mtriple=armv5e-none-linux-gnueabi | FileCheck %s
      2 ; PR8986: PostRA antidependence breaker must respect "earlyclobber".
      3 ; armv5e generates mulv5 that cannot used the same reg for src/dest.
      4 
      5 ; ModuleID = '<stdin>'
      6 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32"
      7 target triple = "armv5e-none-linux-gnueabi"
      8 
      9 define hidden fastcc void @storeAtts() nounwind {
     10 entry:
     11   %.SV116 = alloca i8**
     12   br i1 undef, label %meshBB520, label %meshBB464
     13 
     14 bb15:                                             ; preds = %meshBB424
     15   br i1 undef, label %bb216, label %meshBB396
     16 
     17 bb22:                                             ; preds = %meshBB396
     18   br label %cBB564
     19 
     20 cBB564:                                           ; preds = %cBB564, %bb22
     21   br label %cBB564
     22 
     23 poolStoreString.exit.thread:                      ; preds = %meshBB424
     24   ret void
     25 
     26 bb78:                                             ; preds = %meshBB412
     27   unreachable
     28 
     29 bb129:                                            ; preds = %meshBB540
     30   br i1 undef, label %bb131.loopexit, label %meshBB540
     31 
     32 bb131.loopexit:                                   ; preds = %bb129
     33   br label %bb131
     34 
     35 bb131:                                            ; preds = %bb135, %bb131.loopexit
     36   br i1 undef, label %bb134, label %meshBB396
     37 
     38 bb134:                                            ; preds = %bb131
     39   unreachable
     40 
     41 bb135:                                            ; preds = %meshBB396
     42   %uriHash.1.phi.load = load i32, i32* undef
     43   %.load120 = load i8**, i8*** %.SV116
     44   %.phi24 = load i8, i8* null
     45   %.phi26 = load i8*, i8** null
     46   store i8 %.phi24, i8* %.phi26, align 1
     47   %0 = getelementptr inbounds i8, i8* %.phi26, i32 1
     48   store i8* %0, i8** %.load120, align 4
     49   ; CHECK: mul [[REGISTER:lr|r[0-9]+]],
     50   ; CHECK-NOT: [[REGISTER]],
     51   ; CHECK: {{(lr|r[0-9]+)$}}
     52   %1 = mul i32 %uriHash.1.phi.load, 1000003
     53   %2 = xor i32 0, %1
     54   store i32 %2, i32* null
     55   %3 = load i8, i8* null, align 1
     56   %4 = icmp eq i8 %3, 0
     57   store i8* %0, i8** undef
     58   br i1 %4, label %meshBB472, label %bb131
     59 
     60 bb212:                                            ; preds = %meshBB540
     61   unreachable
     62 
     63 bb216:                                            ; preds = %bb15
     64   ret void
     65 
     66 meshBB396:                                        ; preds = %bb131, %bb15
     67   br i1 undef, label %bb135, label %bb22
     68 
     69 meshBB412:                                        ; preds = %meshBB464
     70   br i1 undef, label %meshBB504, label %bb78
     71 
     72 meshBB424:                                        ; preds = %meshBB464
     73   br i1 undef, label %poolStoreString.exit.thread, label %bb15
     74 
     75 meshBB464:                                        ; preds = %entry
     76   br i1 undef, label %meshBB424, label %meshBB412
     77 
     78 meshBB472:                                        ; preds = %meshBB504, %bb135
     79   unreachable
     80 
     81 meshBB504:                                        ; preds = %meshBB412
     82   br label %meshBB472
     83 
     84 meshBB520:                                        ; preds = %entry
     85   br label %meshBB540
     86 
     87 meshBB540:                                        ; preds = %meshBB520, %bb129
     88   br i1 undef, label %bb212, label %bb129
     89 }
     90