Home | History | Annotate | Download | only in ARM
      1 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 | FileCheck %s
      2 
      3 ; subs r4, #1
      4 ; cmp r4, 0
      5 ; bgt
      6 ; cmp cannot be optimized away since it will clear the overflow bit.
      7 ; gt / ge, lt, le conditions all depend on V bit.
      8 ; rdar://9172742
      9 
     10 define i32 @t() nounwind {
     11 ; CHECK-LABEL: t:
     12 entry:
     13   br label %bb2
     14 
     15 bb:                                               ; preds = %bb2
     16   %0 = tail call i32 @rand() nounwind
     17   %1 = icmp eq i32 %0, 50
     18   br i1 %1, label %bb3, label %bb1
     19 
     20 bb1:                                              ; preds = %bb
     21   %tmp = tail call i32 @puts() nounwind
     22   %indvar.next = add i32 %indvar, 1
     23   br label %bb2
     24 
     25 bb2:                                              ; preds = %bb1, %entry
     26 ; CHECK: bb2
     27 ; CHECK: subs [[REG:r[0-9]+]], #1
     28 ; CHECK: cmp [[REG]], #0
     29 ; CHECK: ble
     30   %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ]
     31   %tries.0 = sub i32 2147483647, %indvar
     32   %tmp1 = icmp sgt i32 %tries.0, 0
     33   br i1 %tmp1, label %bb, label %bb3
     34 
     35 bb3:                                              ; preds = %bb2, %bb
     36   ret i32 0
     37 }
     38 
     39 declare i32 @rand()
     40 
     41 declare i32 @puts() nounwind
     42