1 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ALL 2 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ALL 3 4 ; FIXME Add tests for thumbv7, they currently fail MI verification because 5 ; of a mismatch in register classes in uses. 6 7 ; This test verifies that load/store instructions are properly generated, 8 ; and that they pass MI verification (wasn't the case until 2013-06-08). 9 10 @a = global i8 1, align 1 11 @b = global i16 2, align 2 12 @c = global i32 4, align 4 13 14 ; ldr 15 16 define i8 @t1() nounwind uwtable ssp { 17 ; ALL: @t1 18 ; ALL: ldrb 19 ; ALL: add 20 %1 = load i8, i8* @a, align 1 21 %2 = add nsw i8 %1, 1 22 ret i8 %2 23 } 24 25 define i16 @t2() nounwind uwtable ssp { 26 ; ALL: @t2 27 ; ALL: ldrh 28 ; ALL: add 29 %1 = load i16, i16* @b, align 2 30 %2 = add nsw i16 %1, 1 31 ret i16 %2 32 } 33 34 define i32 @t3() nounwind uwtable ssp { 35 ; ALL: @t3 36 ; ALL: ldr 37 ; ALL: add 38 %1 = load i32, i32* @c, align 4 39 %2 = add nsw i32 %1, 1 40 ret i32 %2 41 } 42 43 ; str 44 45 define void @t4(i8 %v) nounwind uwtable ssp { 46 ; ALL: @t4 47 ; ALL: add 48 ; ALL: strb 49 %1 = add nsw i8 %v, 1 50 store i8 %1, i8* @a, align 1 51 ret void 52 } 53 54 define void @t5(i16 %v) nounwind uwtable ssp { 55 ; ALL: @t5 56 ; ALL: add 57 ; ALL: strh 58 %1 = add nsw i16 %v, 1 59 store i16 %1, i16* @b, align 2 60 ret void 61 } 62 63 define void @t6(i32 %v) nounwind uwtable ssp { 64 ; ALL: @t6 65 ; ALL: add 66 ; ALL: str 67 %1 = add nsw i32 %v, 1 68 store i32 %1, i32* @c, align 4 69 ret void 70 } 71
