1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s 2 3 define <4 x i32> @test1(<4 x i32> %a) nounwind { 4 ; CHECK-LABEL: test1: 5 ; CHECK: vabs.s32 q 6 %tmp1neg = sub <4 x i32> zeroinitializer, %a 7 %b = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1> 8 %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg 9 ret <4 x i32> %abs 10 } 11 12 define <4 x i32> @test2(<4 x i32> %a) nounwind { 13 ; CHECK-LABEL: test2: 14 ; CHECK: vabs.s32 q 15 %tmp1neg = sub <4 x i32> zeroinitializer, %a 16 %b = icmp sge <4 x i32> %a, zeroinitializer 17 %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg 18 ret <4 x i32> %abs 19 } 20 21 define <8 x i16> @test3(<8 x i16> %a) nounwind { 22 ; CHECK-LABEL: test3: 23 ; CHECK: vabs.s16 q 24 %tmp1neg = sub <8 x i16> zeroinitializer, %a 25 %b = icmp sgt <8 x i16> %a, zeroinitializer 26 %abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg 27 ret <8 x i16> %abs 28 } 29 30 define <16 x i8> @test4(<16 x i8> %a) nounwind { 31 ; CHECK-LABEL: test4: 32 ; CHECK: vabs.s8 q 33 %tmp1neg = sub <16 x i8> zeroinitializer, %a 34 %b = icmp slt <16 x i8> %a, zeroinitializer 35 %abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a 36 ret <16 x i8> %abs 37 } 38 39 define <4 x i32> @test5(<4 x i32> %a) nounwind { 40 ; CHECK-LABEL: test5: 41 ; CHECK: vabs.s32 q 42 %tmp1neg = sub <4 x i32> zeroinitializer, %a 43 %b = icmp sle <4 x i32> %a, zeroinitializer 44 %abs = select <4 x i1> %b, <4 x i32> %tmp1neg, <4 x i32> %a 45 ret <4 x i32> %abs 46 } 47 48 define <2 x i32> @test6(<2 x i32> %a) nounwind { 49 ; CHECK-LABEL: test6: 50 ; CHECK: vabs.s32 d 51 %tmp1neg = sub <2 x i32> zeroinitializer, %a 52 %b = icmp sgt <2 x i32> %a, <i32 -1, i32 -1> 53 %abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg 54 ret <2 x i32> %abs 55 } 56 57 define <2 x i32> @test7(<2 x i32> %a) nounwind { 58 ; CHECK-LABEL: test7: 59 ; CHECK: vabs.s32 d 60 %tmp1neg = sub <2 x i32> zeroinitializer, %a 61 %b = icmp sge <2 x i32> %a, zeroinitializer 62 %abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg 63 ret <2 x i32> %abs 64 } 65 66 define <4 x i16> @test8(<4 x i16> %a) nounwind { 67 ; CHECK-LABEL: test8: 68 ; CHECK: vabs.s16 d 69 %tmp1neg = sub <4 x i16> zeroinitializer, %a 70 %b = icmp sgt <4 x i16> %a, zeroinitializer 71 %abs = select <4 x i1> %b, <4 x i16> %a, <4 x i16> %tmp1neg 72 ret <4 x i16> %abs 73 } 74 75 define <8 x i8> @test9(<8 x i8> %a) nounwind { 76 ; CHECK-LABEL: test9: 77 ; CHECK: vabs.s8 d 78 %tmp1neg = sub <8 x i8> zeroinitializer, %a 79 %b = icmp slt <8 x i8> %a, zeroinitializer 80 %abs = select <8 x i1> %b, <8 x i8> %tmp1neg, <8 x i8> %a 81 ret <8 x i8> %abs 82 } 83 84 define <2 x i32> @test10(<2 x i32> %a) nounwind { 85 ; CHECK-LABEL: test10: 86 ; CHECK: vabs.s32 d 87 %tmp1neg = sub <2 x i32> zeroinitializer, %a 88 %b = icmp sle <2 x i32> %a, zeroinitializer 89 %abs = select <2 x i1> %b, <2 x i32> %tmp1neg, <2 x i32> %a 90 ret <2 x i32> %abs 91 } 92 93 ;; Check that absdiff patterns as emitted by log2 shuffles are 94 ;; matched by VABD. 95 96 define <4 x i32> @test11(<4 x i16> %a, <4 x i16> %b) nounwind { 97 ; CHECK-LABEL: test11: 98 ; CHECK: vabdl.u16 q 99 %zext1 = zext <4 x i16> %a to <4 x i32> 100 %zext2 = zext <4 x i16> %b to <4 x i32> 101 %diff = sub <4 x i32> %zext1, %zext2 102 %shift1 = ashr <4 x i32> %diff, <i32 31, i32 31, i32 31, i32 31> 103 %add1 = add <4 x i32> %shift1, %diff 104 %res = xor <4 x i32> %shift1, %add1 105 ret <4 x i32> %res 106 } 107 define <8 x i16> @test12(<8 x i8> %a, <8 x i8> %b) nounwind { 108 ; CHECK-LABEL: test12: 109 ; CHECK: vabdl.u8 q 110 %zext1 = zext <8 x i8> %a to <8 x i16> 111 %zext2 = zext <8 x i8> %b to <8 x i16> 112 %diff = sub <8 x i16> %zext1, %zext2 113 %shift1 = ashr <8 x i16> %diff,<i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> 114 %add1 = add <8 x i16> %shift1, %diff 115 %res = xor <8 x i16> %shift1, %add1 116 ret <8 x i16> %res 117 } 118 119 define <2 x i64> @test13(<2 x i32> %a, <2 x i32> %b) nounwind { 120 ; CHECK-LABEL: test13: 121 ; CHECK: vabdl.u32 q 122 %zext1 = zext <2 x i32> %a to <2 x i64> 123 %zext2 = zext <2 x i32> %b to <2 x i64> 124 %diff = sub <2 x i64> %zext1, %zext2 125 %shift1 = ashr <2 x i64> %diff,<i64 63, i64 63> 126 %add1 = add <2 x i64> %shift1, %diff 127 %res = xor <2 x i64> %shift1, %add1 128 ret <2 x i64> %res 129 } 130
