1 ; RUN: llc -march=hexagon --filetype=obj < %s -o - | llvm-objdump -d - | FileCheck %s 2 3 ; Function Attrs: nounwind 4 define i32 @cmpeq(i32 %i) #0 { 5 entry: 6 %i.addr = alloca i32, align 4 7 store i32 %i, i32* %i.addr, align 4 8 %0 = load i32, i32* %i.addr, align 4 9 %1 = call i32 @llvm.hexagon.C2.cmpeq(i32 %0, i32 1) 10 ret i32 %1 11 } 12 ; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}}, r{{[0-9]}}) 13 14 ; Function Attrs: nounwind readnone 15 declare i32 @llvm.hexagon.C2.cmpeq(i32, i32) #1 16 17 ; Function Attrs: nounwind 18 define i32 @cmpgt(i32 %i) #0 { 19 entry: 20 %i.addr = alloca i32, align 4 21 store i32 %i, i32* %i.addr, align 4 22 %0 = load i32, i32* %i.addr, align 4 23 %1 = call i32 @llvm.hexagon.C2.cmpgt(i32 %0, i32 2) 24 ret i32 %1 25 } 26 ; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}}, r{{[0-9]}}) 27 28 ; Function Attrs: nounwind readnone 29 declare i32 @llvm.hexagon.C2.cmpgt(i32, i32) #1 30 31 ; Function Attrs: nounwind 32 define i32 @cmpgtu(i32 %i) #0 { 33 entry: 34 %i.addr = alloca i32, align 4 35 store i32 %i, i32* %i.addr, align 4 36 %0 = load i32, i32* %i.addr, align 4 37 %1 = call i32 @llvm.hexagon.C2.cmpgtu(i32 %0, i32 3) 38 ret i32 %1 39 } 40 ; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}}, r{{[0-9]}}) 41 42 ; Function Attrs: nounwind readnone 43 declare i32 @llvm.hexagon.C2.cmpgtu(i32, i32) #1 44 45 ; Function Attrs: nounwind 46 define i32 @cmplt(i32 %i) #0 { 47 entry: 48 %i.addr = alloca i32, align 4 49 store i32 %i, i32* %i.addr, align 4 50 %0 = load i32, i32* %i.addr, align 4 51 %1 = call i32 @llvm.hexagon.C2.cmplt(i32 %0, i32 4) 52 ret i32 %1 53 } 54 ; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}}, r{{[0-9]}}) 55 56 ; Function Attrs: nounwind readnone 57 declare i32 @llvm.hexagon.C2.cmplt(i32, i32) #1 58 59 ; Function Attrs: nounwind 60 define i32 @cmpltu(i32 %i) #0 { 61 entry: 62 %i.addr = alloca i32, align 4 63 store i32 %i, i32* %i.addr, align 4 64 %0 = load i32, i32* %i.addr, align 4 65 %1 = call i32 @llvm.hexagon.C2.cmpltu(i32 %0, i32 5) 66 ret i32 %1 67 } 68 ; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}}, r{{[0-9]}}) 69 70 ; Function Attrs: nounwind readnone 71 declare i32 @llvm.hexagon.C2.cmpltu(i32, i32) #1 72 73 ; Function Attrs: nounwind 74 define i32 @cmpeqi(i32 %i) #0 { 75 entry: 76 %i.addr = alloca i32, align 4 77 store i32 %i, i32* %i.addr, align 4 78 %0 = load i32, i32* %i.addr, align 4 79 %1 = call i32 @llvm.hexagon.C2.cmpeqi(i32 %0, i32 10) 80 ret i32 %1 81 } 82 ; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}}, {{.*}}#10) 83 84 ; Function Attrs: nounwind readnone 85 declare i32 @llvm.hexagon.C2.cmpeqi(i32, i32) #1 86 87 ; Function Attrs: nounwind 88 define i32 @cmpgti(i32 %i) #0 { 89 entry: 90 %i.addr = alloca i32, align 4 91 store i32 %i, i32* %i.addr, align 4 92 %0 = load i32, i32* %i.addr, align 4 93 %1 = call i32 @llvm.hexagon.C2.cmpgti(i32 %0, i32 20) 94 ret i32 %1 95 } 96 ; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}}, {{.*}}#20) 97 98 ; Function Attrs: nounwind readnone 99 declare i32 @llvm.hexagon.C2.cmpgti(i32, i32) #1 100 101 ; Function Attrs: nounwind 102 define i32 @cmpgtui(i32 %i) #0 { 103 entry: 104 %i.addr = alloca i32, align 4 105 store i32 %i, i32* %i.addr, align 4 106 %0 = load i32, i32* %i.addr, align 4 107 %1 = call i32 @llvm.hexagon.C2.cmpgtui(i32 %0, i32 40) 108 ret i32 %1 109 } 110 ; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}}, {{.*}}#40) 111 112 ; Function Attrs: nounwind readnone 113 declare i32 @llvm.hexagon.C2.cmpgtui(i32, i32) #1 114 115 ; Function Attrs: nounwind 116 define i32 @cmpgei(i32 %i) #0 { 117 entry: 118 %i.addr = alloca i32, align 4 119 store i32 %i, i32* %i.addr, align 4 120 %0 = load i32, i32* %i.addr, align 4 121 %1 = call i32 @llvm.hexagon.C2.cmpgei(i32 %0, i32 3) 122 ret i32 %1 123 } 124 ; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}}, {{.*}}#2) 125 126 ; Function Attrs: nounwind readnone 127 declare i32 @llvm.hexagon.C2.cmpgei(i32, i32) #1 128 129 ; Function Attrs: nounwind 130 define i32 @cmpgeu(i32 %i) #0 { 131 entry: 132 %i.addr = alloca i32, align 4 133 store i32 %i, i32* %i.addr, align 4 134 %0 = load i32, i32* %i.addr, align 4 135 %1 = call i32 @llvm.hexagon.C2.cmpgeui(i32 %0, i32 3) 136 ret i32 %1 137 } 138 ; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}}, {{.*}}#2) 139 140 ; Function Attrs: nounwind readnone 141 declare i32 @llvm.hexagon.C2.cmpgeui(i32, i32) #1 142 143 ; Function Attrs: nounwind 144 define i32 @cmpgeu0(i32 %i) #0 { 145 entry: 146 %i.addr = alloca i32, align 4 147 store i32 %i, i32* %i.addr, align 4 148 %0 = load i32, i32* %i.addr, align 4 149 %1 = call i32 @llvm.hexagon.C2.cmpgeui(i32 %0, i32 0) 150 ret i32 %1 151 } 152 ; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}}, r{{[0-9]}}) 153 154 155 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } 156 attributes #1 = { nounwind readnone } 157 158 !llvm.ident = !{!0} 159 160 !0 = !{!"Clang 3.1"} 161 162
