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      1 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
      2 ; RUN:     < %s | FileCheck %s 
      3 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
      4 ; RUN:     < %s | FileCheck %s
      5 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
      6 ; RUN:     < %s | FileCheck %s -check-prefix=mips32r2 
      7 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
      8 ; RUN:     < %s | FileCheck %s -check-prefix=mips32
      9 
     10 @f = common global float 0.000000e+00, align 4
     11 @de = common global double 0.000000e+00, align 8
     12 
     13 ; Function Attrs: nounwind
     14 define void @f1() #0 {
     15 entry:
     16   store float 0x3FFA76C8C0000000, float* @f, align 4
     17   ret void
     18 ; CHECK:  .ent  f1
     19 ; CHECK:  lui  $[[REG1:[0-9]+]], 16339
     20 ; CHECK:  ori  $[[REG2:[0-9]+]], $[[REG1]], 46662
     21 ; CHECK:  mtc1  $[[REG2]], $f[[REG3:[0-9]+]]
     22 ; CHECK:  lw  $[[REG4:[0-9]+]], %got(f)(${{[0-9]+}})
     23 ; CHECK:  swc1  $f[[REG3]], 0($[[REG4]])
     24 ; CHECK:   .end  f1
     25 
     26 }
     27 
     28 ; Function Attrs: nounwind
     29 define void @d1() #0 {
     30 entry:
     31   store double 1.234567e+00, double* @de, align 8
     32 ; mip32r2:  .ent  d1
     33 ; mips32r2:  lui  $[[REG1a:[0-9]+]], 16371
     34 ; mips32r2:  ori  $[[REG2a:[0-9]+]], $[[REG1a]], 49353
     35 ; mips32r2:  lui  $[[REG1b:[0-9]+]], 21403
     36 ; mips32r2:  ori  $[[REG2b:[0-9]+]], $[[REG1b]], 34951
     37 ; mips32r2:  mtc1  $[[REG2b]], $f[[REG3:[0-9]+]]
     38 ; mips32r2:  mthc1  $[[REG2a]], $f[[REG3]]
     39 ; mips32r2:  sdc1  $f[[REG3]], 0(${{[0-9]+}})
     40 ; mips32r2:  .end  d1
     41 ; mips32:  .ent  d1
     42 ; mips32:  lui  $[[REG1a:[0-9]+]], 16371
     43 ; mips32:  ori  $[[REG2a:[0-9]+]], $[[REG1a]], 49353
     44 ; mips32:  lui  $[[REG1b:[0-9]+]], 21403
     45 ; mips32:  ori  $[[REG2b:[0-9]+]], $[[REG1b]], 34951
     46 ; mips32:  mtc1  $[[REG2b]], $f[[REG3:[0-9]+]]
     47 ; mips32:  mtc1  $[[REG2a]], $f{{[0-9]+}}
     48 ; mips32:  sdc1  $f[[REG3]], 0(${{[0-9]+}})
     49 ; mips32:  .end  d1
     50 
     51   ret void
     52 }
     53 
     54 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
     55