1 ; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefixes=ALL,MIPS32-R1-R2,MIPS32-GT-R1 %s 2 ; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefixes=ALL,MIPS32-R1-R2,MIPS32-GT-R1 %s 3 ; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefixes=ALL,MIPS32-R6,MIPS32-GT-R1 %s 4 ; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefixes=ALL,MIPS4 %s 5 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s 6 ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s 7 ; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s 8 ; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS64 %s 9 10 ; Prefixes: 11 ; ALL - All 12 ; MIPS32-GT-R1 - MIPS64r1 and above (does not include MIPS64's) 13 ; MIPS64-GT-R1 - MIPS64r1 and above 14 15 define i32 @ctlz_i32(i32 signext %X) nounwind readnone { 16 entry: 17 ; ALL-LABEL: ctlz_i32: 18 19 ; MIPS4-NOT: clz 20 21 ; MIPS32-GT-R1: clz $2, $4 22 23 ; MIPS64-GT-R1: clz $2, $4 24 25 ; MICROMIPS64: clz $2, $4 26 27 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true) 28 ret i32 %tmp1 29 } 30 31 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone 32 33 define i32 @ctlo_i32(i32 signext %X) nounwind readnone { 34 entry: 35 ; ALL-LABEL: ctlo_i32: 36 37 ; MIPS4-NOT: clo 38 39 ; MIPS32-GT-R1: clo $2, $4 40 41 ; MIPS64-GT-R1: clo $2, $4 42 43 ; MICROMIPS64: clo $2, $4 44 45 %neg = xor i32 %X, -1 46 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true) 47 ret i32 %tmp1 48 } 49 50 define i64 @ctlz_i64(i64 %X) nounwind readnone { 51 entry: 52 ; ALL-LABEL: ctlz_i64: 53 54 ; MIPS4-NOT: dclz 55 56 ; MIPS32-GT-R1-DAG: clz $[[R0:[0-9]+]], $4 57 ; MIPS32-GT-R1-DAG: clz $[[R1:[0-9]+]], $5 58 ; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32 59 ; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $5 60 ; MIPS32-R6-DAG: seleqz $[[R5:[0-9]+]], $[[R2]], $5 61 ; MIPS32-R6-DAG: selnez $[[R6:[0-9]+]], $[[R1]], $5 62 ; MIPS32-R6-DAG: or $2, $[[R6]], $[[R5]] 63 ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0 64 65 ; MIPS64-GT-R1: dclz $2, $4 66 ; MICROMIPS64: dclz $2, $4 67 68 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) 69 ret i64 %tmp1 70 } 71 72 declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone 73 74 define i64 @ctlo_i64(i64 %X) nounwind readnone { 75 entry: 76 ; ALL-LABEL: ctlo_i64: 77 78 ; MIPS4-NOT: dclo 79 80 ; MIPS32-GT-R1-DAG: clo $[[R0:[0-9]+]], $4 81 ; MIPS32-GT-R1-DAG: clo $[[R1:[0-9]+]], $5 82 ; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32 83 ; MIPS32-GT-R1-DAG: addiu $[[R3:[0-9]+]], $zero, -1 84 ; MIPS32-GT-R1-DAG: xor $[[R4:[0-9]+]], $5, $[[R3]] 85 ; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $[[R4]] 86 ; MIPS32-R6-DAG: selnez $[[R5:[0-9]+]], $[[R1]], $[[R4]] 87 ; MIPS32-R6-DAG: seleqz $[[R6:[0-9]+]], $[[R2]], $[[R4]] 88 ; MIPS32-R6-DAG: or $2, $[[R5]], $[[R6]] 89 ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0 90 91 ; MIPS64-GT-R1: dclo $2, $4 92 ; MICROMIPS64: dclo $2, $4 93 94 %neg = xor i64 %X, -1 95 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) 96 ret i64 %tmp1 97 } 98
