1 ; Test all important variants of the 'ret' instruction. 2 ; 3 ; For non-void returns it is necessary to have something to return so we also 4 ; test constant generation here. 5 ; 6 ; We'll test pointer returns in a separate file since the relocation model 7 ; affects it and it's undesirable to repeat the non-pointer returns for each 8 ; relocation model. 9 10 ; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,NO-MTHC1,NOT-R6 11 ; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 12 ; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 13 ; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 14 ; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,R6C 15 ; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 16 ; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 17 ; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 18 ; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 19 ; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 20 21 ; FIXME: for the test ret_double_0x0, the delay slot of jr cannot be filled 22 ; as mthc1 has unmodeled side effects. This is an artifact of our backend. 23 ; Force the delay slot filler off to check that the sequence jr $ra; nop is 24 ; turned into jic 0, $ra. 25 26 ; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C 27 28 define void @ret_void() { 29 ; ALL-LABEL: ret_void: 30 31 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR 32 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 33 ; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC 34 35 ret void 36 } 37 38 define i8 @ret_i8() { 39 ; ALL-LABEL: ret_i8: 40 ; ALL-DAG: addiu $2, $zero, 3 41 42 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR 43 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 44 45 ret i8 3 46 } 47 48 define i16 @ret_i16_3() { 49 ; ALL-LABEL: ret_i16_3: 50 ; ALL-DAG: addiu $2, $zero, 3 51 52 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR 53 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 54 55 ret i16 3 56 } 57 58 define i16 @ret_i16_256() { 59 ; ALL-LABEL: ret_i16_256: 60 ; ALL-DAG: addiu $2, $zero, 256 61 62 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR 63 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 64 65 ret i16 256 66 } 67 68 define i16 @ret_i16_257() { 69 ; ALL-LABEL: ret_i16_257: 70 ; ALL-DAG: addiu $2, $zero, 257 71 72 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR 73 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 74 75 ret i16 257 76 } 77 78 define i32 @ret_i32_257() { 79 ; ALL-LABEL: ret_i32_257: 80 ; ALL-DAG: addiu $2, $zero, 257 81 82 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR 83 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 84 85 ret i32 257 86 } 87 88 define i32 @ret_i32_65536() { 89 ; ALL-LABEL: ret_i32_65536: 90 ; ALL-DAG: lui $2, 1 91 92 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR 93 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 94 95 ret i32 65536 96 } 97 98 define i32 @ret_i32_65537() { 99 ; ALL-LABEL: ret_i32_65537: 100 ; ALL: lui $[[T0:[0-9]+]], 1 101 ; ALL-DAG: ori $2, $[[T0]], 1 102 103 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR 104 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 105 106 ret i32 65537 107 } 108 109 define i64 @ret_i64_65537() { 110 ; ALL-LABEL: ret_i64_65537: 111 ; ALL: lui $[[T0:[0-9]+]], 1 112 113 ; GPR32-DAG: ori $3, $[[T0]], 1 114 ; GPR32-DAG: addiu $2, $zero, 0 115 116 ; GPR64-DAG: daddiu $2, $[[T0]], 1 117 118 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR 119 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 120 121 ret i64 65537 122 } 123 124 define i64 @ret_i64_281479271677952() { 125 ; ALL-LABEL: ret_i64_281479271677952: 126 ; ALL-DAG: lui $[[T0:[0-9]+]], 1 127 128 ; GPR32-DAG: ori $2, $[[T0]], 1 129 ; GPR32-DAG: addiu $3, $zero, 0 130 131 ; GPR64-DAG: daddiu $[[T1:[0-9]+]], $[[T0]], 1 132 ; GPR64-DAG: dsll $2, $[[T1]], 32 133 134 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR 135 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 136 137 ret i64 281479271677952 138 } 139 140 define i64 @ret_i64_281479271809026() { 141 ; ALL-LABEL: ret_i64_281479271809026: 142 ; GPR32-DAG: lui $[[T0:[0-9]+]], 1 143 ; GPR32-DAG: lui $[[T1:[0-9]+]], 2 144 ; GPR32-DAG: ori $2, $[[T0]], 1 145 ; GPR32-DAG: ori $3, $[[T1]], 2 146 147 ; GPR64-DAG: ori $[[T0:[0-9]+]], $zero, 32769 148 ; GPR64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 16 149 ; GPR64-DAG: daddiu $[[T0:[0-9]+]], $[[T0]], -32767 150 ; GPR64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 17 151 ; GPR64-DAG: daddiu $2, $[[T1]], 2 152 153 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR 154 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 155 156 ret i64 281479271809026 157 } 158 159 define float @ret_float_0x0() { 160 ; ALL-LABEL: ret_float_0x0: 161 162 ; NO-MTHC1-DAG: mtc1 $zero, $f0 163 164 ; MTHC1-DAG: mtc1 $zero, $f0 165 166 ; DMTC-DAG: dmtc1 $zero, $f0 167 168 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR 169 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 170 171 ret float 0x0000000000000000 172 } 173 174 define float @ret_float_0x3() { 175 ; ALL-LABEL: ret_float_0x3: 176 177 ; Use a constant pool 178 ; O32-DAG: lwc1 $f0, %lo($CPI 179 ; N64-DAG: lwc1 $f0, %got_ofst($CPI 180 181 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR 182 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 183 ; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC 184 185 ; float constants are written as double constants 186 ret float 0x36b8000000000000 187 } 188 189 define double @ret_double_0x0() { 190 ; ALL-LABEL: ret_double_0x0: 191 192 ; NO-MTHC1-DAG: mtc1 $zero, $f0 193 ; NO-MTHC1-DAG: mtc1 $zero, $f1 194 195 ; MTHC1-DAG: mtc1 $zero, $f0 196 ; MTHC1-DAG: mthc1 $zero, $f0 197 198 ; DMTC-DAG: dmtc1 $zero, $f0 199 200 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR 201 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 202 ; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC 203 204 ret double 0x0000000000000000 205 } 206 207 define double @ret_double_0x3() { 208 ; ALL-LABEL: ret_double_0x3: 209 210 ; Use a constant pool 211 ; O32-DAG: ldc1 $f0, %lo($CPI 212 ; N64-DAG: ldc1 $f0, %got_ofst($CPI 213 214 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR 215 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 216 ; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC 217 218 ret double 0x0000000000000003 219 } 220
