1 ; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ 2 ; RUN: -check-prefixes=ALL,NOT-R6,GP32 3 ; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ 4 ; RUN: -check-prefixes=ALL,NOT-R6,GP32 5 ; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ 6 ; RUN: -check-prefixes=ALL,NOT-R6,GP32 7 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ 8 ; RUN: -check-prefixes=ALL,NOT-R6,GP32 9 ; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ 10 ; RUN: -check-prefixes=ALL,NOT-R6,GP32 11 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ 12 ; RUN: -check-prefixes=ALL,R6,GP32 13 14 ; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ 15 ; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 16 ; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ 17 ; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 18 ; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ 19 ; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 20 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ 21 ; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 22 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ 23 ; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 24 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ 25 ; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 26 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ 27 ; RUN: -check-prefixes=ALL,R6,64R6 28 29 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 30 ; RUN: -check-prefixes=ALL,MMR3,MM32 31 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 32 ; RUN: -check-prefixes=ALL,MMR6,MM32 33 ; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 34 ; RUN: -check-prefixes=ALL,MMR6,MM64 35 36 define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) { 37 entry: 38 ; ALL-LABEL: udiv_i1: 39 40 ; NOT-R6: divu $zero, $4, $5 41 ; NOT-R6: teq $5, $zero, 7 42 ; NOT-R6: mflo $2 43 44 ; R6: divu $2, $4, $5 45 ; R6: teq $5, $zero, 7 46 47 ; MMR3: divu $zero, $4, $5 48 ; MMR3: teq $5, $zero, 7 49 ; MMR3: mflo $2 50 51 ; MMR6: divu $2, $4, $5 52 ; MMR6: teq $5, $zero, 7 53 54 %r = udiv i1 %a, %b 55 ret i1 %r 56 } 57 58 define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) { 59 entry: 60 ; ALL-LABEL: udiv_i8: 61 62 ; NOT-R6: divu $zero, $4, $5 63 ; NOT-R6: teq $5, $zero, 7 64 ; NOT-R6: mflo $2 65 66 ; R6: divu $2, $4, $5 67 ; R6: teq $5, $zero, 7 68 69 ; MMR3: divu $zero, $4, $5 70 ; MMR3: teq $5, $zero, 7 71 ; MMR3: mflo $2 72 73 ; MMR6: divu $2, $4, $5 74 ; MMR6: teq $5, $zero, 7 75 76 %r = udiv i8 %a, %b 77 ret i8 %r 78 } 79 80 define zeroext i16 @udiv_i16(i16 zeroext %a, i16 zeroext %b) { 81 entry: 82 ; ALL-LABEL: udiv_i16: 83 84 ; NOT-R6: divu $zero, $4, $5 85 ; NOT-R6: teq $5, $zero, 7 86 ; NOT-R6: mflo $2 87 88 ; R6: divu $2, $4, $5 89 ; R6: teq $5, $zero, 7 90 91 ; MMR3: divu $zero, $4, $5 92 ; MMR3: teq $5, $zero, 7 93 ; MMR3: mflo $2 94 95 ; MMR6: divu $2, $4, $5 96 ; MMR6: teq $5, $zero, 7 97 98 %r = udiv i16 %a, %b 99 ret i16 %r 100 } 101 102 define signext i32 @udiv_i32(i32 signext %a, i32 signext %b) { 103 entry: 104 ; ALL-LABEL: udiv_i32: 105 106 ; NOT-R6: divu $zero, $4, $5 107 ; NOT-R6: teq $5, $zero, 7 108 ; NOT-R6: mflo $2 109 110 ; R6: divu $2, $4, $5 111 ; R6: teq $5, $zero, 7 112 113 ; MMR3: divu $zero, $4, $5 114 ; MMR3: teq $5, $zero, 7 115 ; MMR3: mflo $2 116 117 ; MMR6: divu $2, $4, $5 118 ; MMR6: teq $5, $zero, 7 119 120 %r = udiv i32 %a, %b 121 ret i32 %r 122 } 123 124 define signext i64 @udiv_i64(i64 signext %a, i64 signext %b) { 125 entry: 126 ; ALL-LABEL: udiv_i64: 127 128 ; GP32: lw $25, %call16(__udivdi3)($gp) 129 130 ; GP64-NOT-R6: ddivu $zero, $4, $5 131 ; GP64-NOT-R6: teq $5, $zero, 7 132 ; GP64-NOT-R6: mflo $2 133 134 ; 64R6: ddivu $2, $4, $5 135 ; 64R6: teq $5, $zero, 7 136 137 ; MM32: lw $25, %call16(__udivdi3)($2) 138 139 ; MM64: ddivu $2, $4, $5 140 ; MM64: teq $5, $zero, 7 141 142 %r = udiv i64 %a, %b 143 ret i64 %r 144 } 145 146 define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) { 147 entry: 148 ; ALL-LABEL: udiv_i128: 149 150 ; GP32: lw $25, %call16(__udivti3)($gp) 151 152 ; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp) 153 ; 64-R6: ld $25, %call16(__udivti3)($gp) 154 155 ; MM32: lw $25, %call16(__udivti3)($2) 156 157 ; MM64: ld $25, %call16(__udivti3)($2) 158 159 %r = udiv i128 %a, %b 160 ret i128 %r 161 } 162
