1 ; Test the MSA integer to floating point conversion intrinsics that are encoded 2 ; with the 2RF instruction format. 3 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s 5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s 6 7 @llvm_mips_ffint_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 8 @llvm_mips_ffint_s_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 9 10 define void @llvm_mips_ffint_s_w_test() nounwind { 11 entry: 12 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ffint_s_w_ARG1 13 %1 = tail call <4 x float> @llvm.mips.ffint.s.w(<4 x i32> %0) 14 store <4 x float> %1, <4 x float>* @llvm_mips_ffint_s_w_RES 15 ret void 16 } 17 18 declare <4 x float> @llvm.mips.ffint.s.w(<4 x i32>) nounwind 19 20 ; CHECK: llvm_mips_ffint_s_w_test: 21 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ffint_s_w_ARG1) 22 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 23 ; CHECK-DAG: ffint_s.w [[WD:\$w[0-9]+]], [[WS]] 24 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ffint_s_w_RES) 25 ; CHECK-DAG: st.w [[WD]], 0([[R2]]) 26 ; CHECK: .size llvm_mips_ffint_s_w_test 27 ; 28 @llvm_mips_ffint_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 29 @llvm_mips_ffint_s_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16 30 31 define void @llvm_mips_ffint_s_d_test() nounwind { 32 entry: 33 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ffint_s_d_ARG1 34 %1 = tail call <2 x double> @llvm.mips.ffint.s.d(<2 x i64> %0) 35 store <2 x double> %1, <2 x double>* @llvm_mips_ffint_s_d_RES 36 ret void 37 } 38 39 declare <2 x double> @llvm.mips.ffint.s.d(<2 x i64>) nounwind 40 41 ; CHECK: llvm_mips_ffint_s_d_test: 42 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ffint_s_d_ARG1) 43 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 44 ; CHECK-DAG: ffint_s.d [[WD:\$w[0-9]+]], [[WS]] 45 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ffint_s_d_RES) 46 ; CHECK-DAG: st.d [[WD]], 0([[R2]]) 47 ; CHECK: .size llvm_mips_ffint_s_d_test 48 ; 49 @llvm_mips_ffint_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 50 @llvm_mips_ffint_u_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 51 52 define void @llvm_mips_ffint_u_w_test() nounwind { 53 entry: 54 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ffint_u_w_ARG1 55 %1 = tail call <4 x float> @llvm.mips.ffint.u.w(<4 x i32> %0) 56 store <4 x float> %1, <4 x float>* @llvm_mips_ffint_u_w_RES 57 ret void 58 } 59 60 declare <4 x float> @llvm.mips.ffint.u.w(<4 x i32>) nounwind 61 62 ; CHECK: llvm_mips_ffint_u_w_test: 63 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ffint_u_w_ARG1) 64 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 65 ; CHECK-DAG: ffint_u.w [[WD:\$w[0-9]+]], [[WS]] 66 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ffint_u_w_RES) 67 ; CHECK-DAG: st.w [[WD]], 0([[R2]]) 68 ; CHECK: .size llvm_mips_ffint_u_w_test 69 ; 70 @llvm_mips_ffint_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 71 @llvm_mips_ffint_u_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16 72 73 define void @llvm_mips_ffint_u_d_test() nounwind { 74 entry: 75 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ffint_u_d_ARG1 76 %1 = tail call <2 x double> @llvm.mips.ffint.u.d(<2 x i64> %0) 77 store <2 x double> %1, <2 x double>* @llvm_mips_ffint_u_d_RES 78 ret void 79 } 80 81 declare <2 x double> @llvm.mips.ffint.u.d(<2 x i64>) nounwind 82 83 ; CHECK: llvm_mips_ffint_u_d_test: 84 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ffint_u_d_ARG1) 85 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 86 ; CHECK-DAG: ffint_u.d [[WD:\$w[0-9]+]], [[WS]] 87 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ffint_u_d_RES) 88 ; CHECK-DAG: st.d [[WD]], 0([[R2]]) 89 ; CHECK: .size llvm_mips_ffint_u_d_test 90 ; 91
