1 ; Test the MSA element insertion intrinsics that are encoded with the ELM 2 ; instruction format. 3 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \ 5 ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 6 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \ 7 ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 8 ; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ 9 ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 10 ; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ 11 ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 12 13 @llvm_mips_insert_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 14 @llvm_mips_insert_b_ARG3 = global i32 27, align 16 15 @llvm_mips_insert_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 16 17 define void @llvm_mips_insert_b_test() nounwind { 18 entry: 19 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_insert_b_ARG1 20 %1 = load i32, i32* @llvm_mips_insert_b_ARG3 21 %2 = tail call <16 x i8> @llvm.mips.insert.b(<16 x i8> %0, i32 1, i32 %1) 22 store <16 x i8> %2, <16 x i8>* @llvm_mips_insert_b_RES 23 ret void 24 } 25 26 declare <16 x i8> @llvm.mips.insert.b(<16 x i8>, i32, i32) nounwind 27 28 ; MIPS-ANY: llvm_mips_insert_b_test: 29 ; MIPS-ANY-DAG: lw [[R1:\$[0-9]+]], 0( 30 ; MIPS-ANY-DAG: ld.b [[R2:\$w[0-9]+]], 0( 31 ; MIPS-ANY-DAG: insert.b [[R2]][1], [[R1]] 32 ; MIPS-ANY-DAG: st.b [[R2]], 0( 33 ; MIPS-ANY: .size llvm_mips_insert_b_test 34 ; 35 @llvm_mips_insert_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 36 @llvm_mips_insert_h_ARG3 = global i32 27, align 16 37 @llvm_mips_insert_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 38 39 define void @llvm_mips_insert_h_test() nounwind { 40 entry: 41 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_insert_h_ARG1 42 %1 = load i32, i32* @llvm_mips_insert_h_ARG3 43 %2 = tail call <8 x i16> @llvm.mips.insert.h(<8 x i16> %0, i32 1, i32 %1) 44 store <8 x i16> %2, <8 x i16>* @llvm_mips_insert_h_RES 45 ret void 46 } 47 48 declare <8 x i16> @llvm.mips.insert.h(<8 x i16>, i32, i32) nounwind 49 50 ; MIPS-ANY: llvm_mips_insert_h_test: 51 ; MIPS-ANY-DAG: lw [[R1:\$[0-9]+]], 0( 52 ; MIPS-ANY-DAG: ld.h [[R2:\$w[0-9]+]], 0( 53 ; MIPS-ANY-DAG: insert.h [[R2]][1], [[R1]] 54 ; MIPS-ANY-DAG: st.h [[R2]], 0( 55 ; MIPS-ANY: .size llvm_mips_insert_h_test 56 ; 57 @llvm_mips_insert_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 58 @llvm_mips_insert_w_ARG3 = global i32 27, align 16 59 @llvm_mips_insert_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 60 61 define void @llvm_mips_insert_w_test() nounwind { 62 entry: 63 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_insert_w_ARG1 64 %1 = load i32, i32* @llvm_mips_insert_w_ARG3 65 %2 = tail call <4 x i32> @llvm.mips.insert.w(<4 x i32> %0, i32 1, i32 %1) 66 store <4 x i32> %2, <4 x i32>* @llvm_mips_insert_w_RES 67 ret void 68 } 69 70 declare <4 x i32> @llvm.mips.insert.w(<4 x i32>, i32, i32) nounwind 71 72 ; MIPS-ANY: llvm_mips_insert_w_test: 73 ; MIPS-ANY-DAG: lw [[R1:\$[0-9]+]], 0( 74 ; MIPS-ANY-DAG: ld.w [[R2:\$w[0-9]+]], 0( 75 ; MIPS-ANY-DAG: insert.w [[R2]][1], [[R1]] 76 ; MIPS-ANY-DAG: st.w [[R2]], 0( 77 ; MIPS-ANY: .size llvm_mips_insert_w_test 78 ; 79 @llvm_mips_insert_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 80 @llvm_mips_insert_d_ARG3 = global i64 27, align 16 81 @llvm_mips_insert_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 82 83 define void @llvm_mips_insert_d_test() nounwind { 84 entry: 85 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_insert_d_ARG1 86 %1 = load i64, i64* @llvm_mips_insert_d_ARG3 87 %2 = tail call <2 x i64> @llvm.mips.insert.d(<2 x i64> %0, i32 1, i64 %1) 88 store <2 x i64> %2, <2 x i64>* @llvm_mips_insert_d_RES 89 ret void 90 } 91 92 declare <2 x i64> @llvm.mips.insert.d(<2 x i64>, i32, i64) nounwind 93 94 ; MIPS-ANY: llvm_mips_insert_d_test: 95 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], 0( 96 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 4( 97 ; MIPS64-DAG: ld [[R1:\$[0-9]+]], 0( 98 ; MIPS32-DAG: ld.w [[R3:\$w[0-9]+]], 99 ; MIPS64-DAG: ld.d [[W1:\$w[0-9]+]], 100 ; MIPS32-DAG: insert.w [[R3]][2], [[R1]] 101 ; MIPS32-DAG: insert.w [[R3]][3], [[R2]] 102 ; MIPS64-DAG: insert.d [[W1]][1], [[R1]] 103 ; MIPS32-DAG: st.w [[R3]], 104 ; MIPS64-DAG: st.d [[W1]], 105 ; MIPS-ANY: .size llvm_mips_insert_d_test 106 ; 107 @llvm_mips_insve_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 108 @llvm_mips_insve_b_ARG3 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 109 @llvm_mips_insve_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 110 111 define void @llvm_mips_insve_b_test() nounwind { 112 entry: 113 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_insve_b_ARG1 114 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_insve_b_ARG3 115 %2 = tail call <16 x i8> @llvm.mips.insve.b(<16 x i8> %0, i32 1, <16 x i8> %1) 116 store <16 x i8> %2, <16 x i8>* @llvm_mips_insve_b_RES 117 ret void 118 } 119 120 declare <16 x i8> @llvm.mips.insve.b(<16 x i8>, i32, <16 x i8>) nounwind 121 122 ; MIPS-ANY: llvm_mips_insve_b_test: 123 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_b_ARG1)( 124 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_b_ARG3)( 125 ; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_insve_b_ARG1)( 126 ; MIPS64-DAG: ld [[R2:\$[0-9]+]], %got_disp(llvm_mips_insve_b_ARG3)( 127 ; MIPS-ANY-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]]) 128 ; MIPS-ANY-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]]) 129 ; MIPS-ANY-DAG: insve.b [[R3]][1], [[R4]][0] 130 ; MIPS-ANY-DAG: st.b [[R3]], 131 ; MIPS-ANY: .size llvm_mips_insve_b_test 132 ; 133 @llvm_mips_insve_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 134 @llvm_mips_insve_h_ARG3 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 135 @llvm_mips_insve_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 136 137 define void @llvm_mips_insve_h_test() nounwind { 138 entry: 139 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_insve_h_ARG1 140 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_insve_h_ARG3 141 %2 = tail call <8 x i16> @llvm.mips.insve.h(<8 x i16> %0, i32 1, <8 x i16> %1) 142 store <8 x i16> %2, <8 x i16>* @llvm_mips_insve_h_RES 143 ret void 144 } 145 146 declare <8 x i16> @llvm.mips.insve.h(<8 x i16>, i32, <8 x i16>) nounwind 147 148 ; MIPS-ANY: llvm_mips_insve_h_test: 149 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_h_ARG1)( 150 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_h_ARG3)( 151 ; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_insve_h_ARG1)( 152 ; MIPS64-DAG: ld [[R2:\$[0-9]+]], %got_disp(llvm_mips_insve_h_ARG3)( 153 ; MIPS-ANY-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]]) 154 ; MIPS-ANY-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R2]]) 155 ; MIPS-ANY-DAG: insve.h [[R3]][1], [[R4]][0] 156 ; MIPS-ANY-DAG: st.h [[R3]], 157 ; MIPS-ANY: .size llvm_mips_insve_h_test 158 ; 159 @llvm_mips_insve_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 160 @llvm_mips_insve_w_ARG3 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 161 @llvm_mips_insve_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 162 163 define void @llvm_mips_insve_w_test() nounwind { 164 entry: 165 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_insve_w_ARG1 166 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_insve_w_ARG3 167 %2 = tail call <4 x i32> @llvm.mips.insve.w(<4 x i32> %0, i32 1, <4 x i32> %1) 168 store <4 x i32> %2, <4 x i32>* @llvm_mips_insve_w_RES 169 ret void 170 } 171 172 declare <4 x i32> @llvm.mips.insve.w(<4 x i32>, i32, <4 x i32>) nounwind 173 174 ; MIPS-ANY: llvm_mips_insve_w_test: 175 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_w_ARG1)( 176 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_w_ARG3)( 177 ; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_insve_w_ARG1)( 178 ; MIPS64-DAG: ld [[R2:\$[0-9]+]], %got_disp(llvm_mips_insve_w_ARG3)( 179 ; MIPS-ANY-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]]) 180 ; MIPS-ANY-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R2]]) 181 ; MIPS-ANY-DAG: insve.w [[R3]][1], [[R4]][0] 182 ; MIPS-ANY-DAG: st.w [[R3]], 183 ; MIPS-ANY: .size llvm_mips_insve_w_test 184 ; 185 @llvm_mips_insve_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 186 @llvm_mips_insve_d_ARG3 = global <2 x i64> <i64 2, i64 3>, align 16 187 @llvm_mips_insve_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 188 189 define void @llvm_mips_insve_d_test() nounwind { 190 entry: 191 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_insve_d_ARG1 192 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_insve_d_ARG3 193 %2 = tail call <2 x i64> @llvm.mips.insve.d(<2 x i64> %0, i32 1, <2 x i64> %1) 194 store <2 x i64> %2, <2 x i64>* @llvm_mips_insve_d_RES 195 ret void 196 } 197 198 declare <2 x i64> @llvm.mips.insve.d(<2 x i64>, i32, <2 x i64>) nounwind 199 200 ; MIPS-ANY: llvm_mips_insve_d_test: 201 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_d_ARG1)( 202 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_d_ARG3)( 203 ; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_insve_d_ARG1)( 204 ; MIPS64-DAG: ld [[R2:\$[0-9]+]], %got_disp(llvm_mips_insve_d_ARG3)( 205 ; MIPS-ANY-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]]) 206 ; MIPS-ANY-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R2]]) 207 ; MIPS-ANY-DAG: insve.d [[R3]][1], [[R4]][0] 208 ; MIPS-ANY-DAG: st.d [[R3]], 209 ; MIPS-ANY: .size llvm_mips_insve_d_test 210 ; 211
