1 ; RUN: llc -march=mips < %s 2 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s 3 ; RUN: llc -march=mipsel < %s 4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s 5 6 ; This test is based on an llvm-stress generated test case with seed=449609655 7 8 ; This test originally failed for MSA with a 9 ; "Comparison requires equal bit widths" assertion. 10 ; The legalizer legalized ; the <4 x i8>'s into <4 x i32>'s, then a call to 11 ; isVSplat() returned the splat value for <i8 -1, i8 -1, ...> as a 32-bit APInt 12 ; (255), but the zeroinitializer splat value as an 8-bit APInt (0). The 13 ; assertion occurred when trying to check the values were bitwise inverses of 14 ; each-other. 15 ; 16 ; It should at least successfully build. 17 18 define void @autogen_SD449609655(i8) { 19 BB: 20 %Cmp = icmp ult i8 -3, %0 21 br label %CF78 22 23 CF78: ; preds = %CF81, %CF78, %BB 24 %Sl31 = select i1 %Cmp, <4 x i8> <i8 -1, i8 -1, i8 -1, i8 -1>, <4 x i8> zeroinitializer 25 br i1 undef, label %CF78, label %CF81 26 27 CF81: ; preds = %CF78 28 br i1 undef, label %CF78, label %CF80 29 30 CF80: ; preds = %CF81 31 %I59 = insertelement <4 x i8> %Sl31, i8 undef, i32 1 32 ret void 33 } 34
