1 ; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON 2 ; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64 3 4 define i64 @addi64(i64 %a, i64 %b) nounwind { 5 entry: 6 ; ALL-LABEL: addi64: 7 ; OCTEON: jr $ra 8 ; OCTEON: baddu $2, $4, $5 9 ; MIPS64: daddu $[[T0:[0-9]+]], $4, $5 10 ; MIPS64: jr $ra 11 ; MIPS64: andi $2, $[[T0]], 255 12 %add = add i64 %a, %b 13 %and = and i64 %add, 255 14 ret i64 %and 15 } 16 17 define i64 @mul(i64 %a, i64 %b) nounwind { 18 entry: 19 ; ALL-LABEL: mul: 20 ; OCTEON: jr $ra 21 ; OCTEON: dmul $2, $4, $5 22 ; MIPS64: dmult $4, $5 23 ; MIPS64: jr $ra 24 ; MIPS64: mflo $2 25 %res = mul i64 %a, %b 26 ret i64 %res 27 } 28 29 define i64 @cmpeq(i64 %a, i64 %b) nounwind { 30 entry: 31 ; ALL-LABEL: cmpeq: 32 ; OCTEON: jr $ra 33 ; OCTEON: seq $2, $4, $5 34 ; MIPS64: xor $[[T0:[0-9]+]], $4, $5 35 ; MIPS64: sltiu $[[T1:[0-9]+]], $[[T0]], 1 36 ; MIPS64: dsll $[[T2:[0-9]+]], $[[T1]], 32 37 ; MIPS64: jr $ra 38 ; MIPS64: dsrl $2, $[[T2]], 32 39 %res = icmp eq i64 %a, %b 40 %res2 = zext i1 %res to i64 41 ret i64 %res2 42 } 43 44 define i64 @cmpeqi(i64 %a) nounwind { 45 entry: 46 ; ALL-LABEL: cmpeqi: 47 ; OCTEON: jr $ra 48 ; OCTEON: seqi $2, $4, 42 49 ; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42 50 ; MIPS64: xor $[[T1:[0-9]+]], $4, $[[T0]] 51 ; MIPS64: sltiu $[[T2:[0-9]+]], $[[T1]], 1 52 ; MIPS64: dsll $[[T3:[0-9]+]], $[[T2]], 32 53 ; MIPS64: jr $ra 54 ; MIPS64: dsrl $2, $[[T3]], 32 55 %res = icmp eq i64 %a, 42 56 %res2 = zext i1 %res to i64 57 ret i64 %res2 58 } 59 60 define i64 @cmpne(i64 %a, i64 %b) nounwind { 61 entry: 62 ; ALL-LABEL: cmpne: 63 ; OCTEON: jr $ra 64 ; OCTEON: sne $2, $4, $5 65 ; MIPS64: xor $[[T0:[0-9]+]], $4, $5 66 ; MIPS64: sltu $[[T1:[0-9]+]], $zero, $[[T0]] 67 ; MIPS64: dsll $[[T2:[0-9]+]], $[[T1]], 32 68 ; MIPS64: jr $ra 69 ; MIPS64: dsrl $2, $[[T2]], 32 70 %res = icmp ne i64 %a, %b 71 %res2 = zext i1 %res to i64 72 ret i64 %res2 73 } 74 75 define i64 @cmpnei(i64 %a) nounwind { 76 entry: 77 ; ALL-LABEL: cmpnei: 78 ; OCTEON: jr $ra 79 ; OCTEON: snei $2, $4, 42 80 ; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42 81 ; MIPS64: xor $[[T1:[0-9]+]], $4, $[[T0]] 82 ; MIPS64: sltu $[[T2:[0-9]+]], $zero, $[[T1]] 83 ; MIPS64: dsll $[[T3:[0-9]+]], $[[T2]], 32 84 ; MIPS64: jr $ra 85 ; MIPS64: dsrl $2, $[[T3]], 32 86 %res = icmp ne i64 %a, 42 87 %res2 = zext i1 %res to i64 88 ret i64 %res2 89 } 90 91 define i64 @bbit0(i64 %a) nounwind { 92 entry: 93 ; ALL-LABEL: bbit0: 94 ; OCTEON: bbit0 $4, 3, $[[BB0:BB[0-9_]+]] 95 ; MIPS64: andi $[[T0:[0-9]+]], $4, 8 96 ; MIPS64: bnez $[[T0]], $[[BB0:BB[0-9_]+]] 97 %bit = and i64 %a, 8 98 %res = icmp eq i64 %bit, 0 99 br i1 %res, label %endif, label %if 100 if: 101 ret i64 48 102 103 endif: 104 ret i64 12 105 } 106 107 define i64 @bbit032(i64 %a) nounwind { 108 entry: 109 ; ALL-LABEL: bbit032: 110 ; OCTEON: bbit032 $4, 3, $[[BB0:BB[0-9_]+]] 111 ; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1 112 ; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35 113 ; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]] 114 ; MIPS64: bnez $[[T2]], $[[BB0:BB[0-9_]+]] 115 %bit = and i64 %a, 34359738368 116 %res = icmp eq i64 %bit, 0 117 br i1 %res, label %endif, label %if 118 if: 119 ret i64 48 120 121 endif: 122 ret i64 12 123 } 124 125 define i64 @bbit1(i64 %a) nounwind { 126 entry: 127 ; ALL-LABEL: bbit1: 128 ; OCTEON: bbit1 $4, 3, $[[BB0:BB[0-9_]+]] 129 ; MIPS64: andi $[[T0:[0-9]+]], $4, 8 130 ; MIPS64: beqz $[[T0]], $[[BB0:BB[0-9_]+]] 131 %bit = and i64 %a, 8 132 %res = icmp ne i64 %bit, 0 133 br i1 %res, label %endif, label %if 134 if: 135 ret i64 48 136 137 endif: 138 ret i64 12 139 } 140 141 define i64 @bbit132(i64 %a) nounwind { 142 entry: 143 ; ALL-LABEL: bbit132: 144 ; OCTEON: bbit132 $4, 3, $[[BB0:BB[0-9_]+]] 145 ; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1 146 ; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35 147 ; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]] 148 ; MIPS64: beqz $[[T2]], $[[BB0:BB[0-9_]+]] 149 %bit = and i64 %a, 34359738368 150 %res = icmp ne i64 %bit, 0 151 br i1 %res, label %endif, label %if 152 if: 153 ret i64 48 154 155 endif: 156 ret i64 12 157 } 158
