1 ; Test sequences that can use RISBG with a zeroed first operand. 2 ; The tests here assume that RISBLG isn't available. 3 ; 4 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s 5 6 ; Test an extraction of bit 0 from a right-shifted value. 7 define i32 @f1(i32 %foo) { 8 ; CHECK-LABEL: f1: 9 ; CHECK: risbg %r2, %r2, 63, 191, 54 10 ; CHECK: br %r14 11 %shr = lshr i32 %foo, 10 12 %and = and i32 %shr, 1 13 ret i32 %and 14 } 15 16 ; ...and again with i64. 17 define i64 @f2(i64 %foo) { 18 ; CHECK-LABEL: f2: 19 ; CHECK: risbg %r2, %r2, 63, 191, 54 20 ; CHECK: br %r14 21 %shr = lshr i64 %foo, 10 22 %and = and i64 %shr, 1 23 ret i64 %and 24 } 25 26 ; Test an extraction of other bits from a right-shifted value. 27 define i32 @f3(i32 %foo) { 28 ; CHECK-LABEL: f3: 29 ; CHECK: risbg %r2, %r2, 60, 189, 42 30 ; CHECK: br %r14 31 %shr = lshr i32 %foo, 22 32 %and = and i32 %shr, 12 33 ret i32 %and 34 } 35 36 ; ...and again with i64. 37 define i64 @f4(i64 %foo) { 38 ; CHECK-LABEL: f4: 39 ; CHECK: risbg %r2, %r2, 60, 189, 42 40 ; CHECK: br %r14 41 %shr = lshr i64 %foo, 22 42 %and = and i64 %shr, 12 43 ret i64 %and 44 } 45 46 ; Test an extraction of most bits from a right-shifted value. 47 ; The range should be reduced to exclude the zeroed high bits. 48 define i32 @f5(i32 %foo) { 49 ; CHECK-LABEL: f5: 50 ; CHECK: risbg %r2, %r2, 34, 188, 62 51 ; CHECK: br %r14 52 %shr = lshr i32 %foo, 2 53 %and = and i32 %shr, -8 54 ret i32 %and 55 } 56 57 ; ...and again with i64. 58 define i64 @f6(i64 %foo) { 59 ; CHECK-LABEL: f6: 60 ; CHECK: risbg %r2, %r2, 2, 188, 62 61 ; CHECK: br %r14 62 %shr = lshr i64 %foo, 2 63 %and = and i64 %shr, -8 64 ret i64 %and 65 } 66 67 ; Try the next value up (mask ....1111001). This needs a separate shift 68 ; and mask. 69 define i32 @f7(i32 %foo) { 70 ; CHECK-LABEL: f7: 71 ; CHECK: srl %r2, 2 72 ; CHECK: nill %r2, 65529 73 ; CHECK: br %r14 74 %shr = lshr i32 %foo, 2 75 %and = and i32 %shr, -7 76 ret i32 %and 77 } 78 79 ; ...and again with i64. 80 define i64 @f8(i64 %foo) { 81 ; CHECK-LABEL: f8: 82 ; CHECK: srlg %r2, %r2, 2 83 ; CHECK: nill %r2, 65529 84 ; CHECK: br %r14 85 %shr = lshr i64 %foo, 2 86 %and = and i64 %shr, -7 87 ret i64 %and 88 } 89 90 ; Test an extraction of bits from a left-shifted value. The range should 91 ; be reduced to exclude the zeroed low bits. 92 define i32 @f9(i32 %foo) { 93 ; CHECK-LABEL: f9: 94 ; CHECK: risbg %r2, %r2, 56, 189, 2 95 ; CHECK: br %r14 96 %shr = shl i32 %foo, 2 97 %and = and i32 %shr, 255 98 ret i32 %and 99 } 100 101 ; ...and again with i64. 102 define i64 @f10(i64 %foo) { 103 ; CHECK-LABEL: f10: 104 ; CHECK: risbg %r2, %r2, 56, 189, 2 105 ; CHECK: br %r14 106 %shr = shl i64 %foo, 2 107 %and = and i64 %shr, 255 108 ret i64 %and 109 } 110 111 ; Try a wrap-around mask (mask ....111100001111). This needs a separate shift 112 ; and mask. 113 define i32 @f11(i32 %foo) { 114 ; CHECK-LABEL: f11: 115 ; CHECK: sll %r2, 2 116 ; CHECK: nill %r2, 65295 117 ; CHECK: br %r14 118 %shr = shl i32 %foo, 2 119 %and = and i32 %shr, -241 120 ret i32 %and 121 } 122 123 ; ...and again with i64. 124 define i64 @f12(i64 %foo) { 125 ; CHECK-LABEL: f12: 126 ; CHECK: sllg %r2, %r2, 2 127 ; CHECK: nill %r2, 65295 128 ; CHECK: br %r14 129 %shr = shl i64 %foo, 2 130 %and = and i64 %shr, -241 131 ret i64 %and 132 } 133 134 ; Test an extraction from a rotated value, no mask wraparound. 135 ; This is equivalent to the lshr case, because the bits from the 136 ; shl are not used. 137 define i32 @f13(i32 %foo) { 138 ; CHECK-LABEL: f13: 139 ; CHECK: risbg %r2, %r2, 56, 188, 46 140 ; CHECK: br %r14 141 %parta = shl i32 %foo, 14 142 %partb = lshr i32 %foo, 18 143 %rotl = or i32 %parta, %partb 144 %and = and i32 %rotl, 248 145 ret i32 %and 146 } 147 148 ; ...and again with i64. 149 define i64 @f14(i64 %foo) { 150 ; CHECK-LABEL: f14: 151 ; CHECK: risbg %r2, %r2, 56, 188, 14 152 ; CHECK: br %r14 153 %parta = shl i64 %foo, 14 154 %partb = lshr i64 %foo, 50 155 %rotl = or i64 %parta, %partb 156 %and = and i64 %rotl, 248 157 ret i64 %and 158 } 159 160 ; Try a case in which only the bits from the shl are used. 161 define i32 @f15(i32 %foo) { 162 ; CHECK-LABEL: f15: 163 ; CHECK: risbg %r2, %r2, 47, 177, 14 164 ; CHECK: br %r14 165 %parta = shl i32 %foo, 14 166 %partb = lshr i32 %foo, 18 167 %rotl = or i32 %parta, %partb 168 %and = and i32 %rotl, 114688 169 ret i32 %and 170 } 171 172 ; ...and again with i64. 173 define i64 @f16(i64 %foo) { 174 ; CHECK-LABEL: f16: 175 ; CHECK: risbg %r2, %r2, 47, 177, 14 176 ; CHECK: br %r14 177 %parta = shl i64 %foo, 14 178 %partb = lshr i64 %foo, 50 179 %rotl = or i64 %parta, %partb 180 %and = and i64 %rotl, 114688 181 ret i64 %and 182 } 183 184 ; Test a 32-bit rotate in which both parts of the OR are needed. 185 ; This needs a separate shift and mask. 186 define i32 @f17(i32 %foo) { 187 ; CHECK-LABEL: f17: 188 ; CHECK: rll %r2, %r2, 4 189 ; CHECK: nilf %r2, 126 190 ; CHECK: br %r14 191 %parta = shl i32 %foo, 4 192 %partb = lshr i32 %foo, 28 193 %rotl = or i32 %parta, %partb 194 %and = and i32 %rotl, 126 195 ret i32 %and 196 } 197 198 ; ...and for i64, where RISBG should do the rotate too. 199 define i64 @f18(i64 %foo) { 200 ; CHECK-LABEL: f18: 201 ; CHECK: risbg %r2, %r2, 57, 190, 4 202 ; CHECK: br %r14 203 %parta = shl i64 %foo, 4 204 %partb = lshr i64 %foo, 60 205 %rotl = or i64 %parta, %partb 206 %and = and i64 %rotl, 126 207 ret i64 %and 208 } 209 210 ; Test an arithmetic shift right in which some of the sign bits are kept. 211 ; This needs a separate shift and mask. 212 define i32 @f19(i32 %foo) { 213 ; CHECK-LABEL: f19: 214 ; CHECK: sra %r2, 28 215 ; CHECK: nilf %r2, 30 216 ; CHECK: br %r14 217 %shr = ashr i32 %foo, 28 218 %and = and i32 %shr, 30 219 ret i32 %and 220 } 221 222 ; ...and again with i64. In this case RISBG is the best way of doing the AND. 223 define i64 @f20(i64 %foo) { 224 ; CHECK-LABEL: f20: 225 ; CHECK: srag [[REG:%r[0-5]]], %r2, 60 226 ; CHECK: risbg %r2, [[REG]], 59, 190, 0 227 ; CHECK: br %r14 228 %shr = ashr i64 %foo, 60 229 %and = and i64 %shr, 30 230 ret i64 %and 231 } 232 233 ; Now try an arithmetic right shift in which the sign bits aren't needed. 234 ; Introduce a second use of %shr so that the ashr doesn't decompose to 235 ; an lshr. 236 define i32 @f21(i32 %foo, i32 *%dest) { 237 ; CHECK-LABEL: f21: 238 ; CHECK: risbg %r2, %r2, 60, 190, 36 239 ; CHECK: br %r14 240 %shr = ashr i32 %foo, 28 241 store i32 %shr, i32 *%dest 242 %and = and i32 %shr, 14 243 ret i32 %and 244 } 245 246 ; ...and again with i64. 247 define i64 @f22(i64 %foo, i64 *%dest) { 248 ; CHECK-LABEL: f22: 249 ; CHECK: risbg %r2, %r2, 60, 190, 4 250 ; CHECK: br %r14 251 %shr = ashr i64 %foo, 60 252 store i64 %shr, i64 *%dest 253 %and = and i64 %shr, 14 254 ret i64 %and 255 } 256 257 ; Check that we use RISBG for shifted values even if the AND is a 258 ; natural zero extension. 259 define i64 @f23(i64 %foo) { 260 ; CHECK-LABEL: f23: 261 ; CHECK: risbg %r2, %r2, 56, 191, 62 262 ; CHECK: br %r14 263 %shr = lshr i64 %foo, 2 264 %and = and i64 %shr, 255 265 ret i64 %and 266 } 267 268 ; Test a case where the AND comes before a rotate. This needs a separate 269 ; mask and rotate. 270 define i32 @f24(i32 %foo) { 271 ; CHECK-LABEL: f24: 272 ; CHECK: nilf %r2, 254 273 ; CHECK: rll %r2, %r2, 29 274 ; CHECK: br %r14 275 %and = and i32 %foo, 254 276 %parta = lshr i32 %and, 3 277 %partb = shl i32 %and, 29 278 %rotl = or i32 %parta, %partb 279 ret i32 %rotl 280 } 281 282 ; ...and again with i64, where a single RISBG is enough. 283 define i64 @f25(i64 %foo) { 284 ; CHECK-LABEL: f25: 285 ; CHECK: risbg %r2, %r2, 57, 187, 3 286 ; CHECK: br %r14 287 %and = and i64 %foo, 14 288 %parta = shl i64 %and, 3 289 %partb = lshr i64 %and, 61 290 %rotl = or i64 %parta, %partb 291 ret i64 %rotl 292 } 293 294 ; Test a wrap-around case in which the AND comes before a rotate. 295 ; This again needs a separate mask and rotate. 296 define i32 @f26(i32 %foo) { 297 ; CHECK-LABEL: f26: 298 ; CHECK: rll %r2, %r2, 5 299 ; CHECK: br %r14 300 %and = and i32 %foo, -49 301 %parta = shl i32 %and, 5 302 %partb = lshr i32 %and, 27 303 %rotl = or i32 %parta, %partb 304 ret i32 %rotl 305 } 306 307 ; ...and again with i64, where a single RISBG is OK. 308 define i64 @f27(i64 %foo) { 309 ; CHECK-LABEL: f27: 310 ; CHECK: risbg %r2, %r2, 55, 180, 5 311 ; CHECK: br %r14 312 %and = and i64 %foo, -49 313 %parta = shl i64 %and, 5 314 %partb = lshr i64 %and, 59 315 %rotl = or i64 %parta, %partb 316 ret i64 %rotl 317 } 318 319 ; Test a case where the AND comes before a shift left. 320 define i32 @f28(i32 %foo) { 321 ; CHECK-LABEL: f28: 322 ; CHECK: risbg %r2, %r2, 32, 173, 17 323 ; CHECK: br %r14 324 %and = and i32 %foo, 32766 325 %shl = shl i32 %and, 17 326 ret i32 %shl 327 } 328 329 ; ...and again with i64. 330 define i64 @f29(i64 %foo) { 331 ; CHECK-LABEL: f29: 332 ; CHECK: risbg %r2, %r2, 0, 141, 49 333 ; CHECK: br %r14 334 %and = and i64 %foo, 32766 335 %shl = shl i64 %and, 49 336 ret i64 %shl 337 } 338 339 ; Test the next shift up from f28, in which the mask should get shortened. 340 define i32 @f30(i32 %foo) { 341 ; CHECK-LABEL: f30: 342 ; CHECK: risbg %r2, %r2, 32, 172, 18 343 ; CHECK: br %r14 344 %and = and i32 %foo, 32766 345 %shl = shl i32 %and, 18 346 ret i32 %shl 347 } 348 349 ; ...and again with i64. 350 define i64 @f31(i64 %foo) { 351 ; CHECK-LABEL: f31: 352 ; CHECK: risbg %r2, %r2, 0, 140, 50 353 ; CHECK: br %r14 354 %and = and i64 %foo, 32766 355 %shl = shl i64 %and, 50 356 ret i64 %shl 357 } 358 359 ; Test a wrap-around case in which the shift left comes after the AND. 360 ; We can't use RISBG for the shift in that case. 361 define i32 @f32(i32 %foo) { 362 ; CHECK-LABEL: f32: 363 ; CHECK: sll %r2 364 ; CHECK: br %r14 365 %and = and i32 %foo, -7 366 %shl = shl i32 %and, 10 367 ret i32 %shl 368 } 369 370 ; ...and again with i64. 371 define i64 @f33(i64 %foo) { 372 ; CHECK-LABEL: f33: 373 ; CHECK: sllg %r2 374 ; CHECK: br %r14 375 %and = and i64 %foo, -7 376 %shl = shl i64 %and, 10 377 ret i64 %shl 378 } 379 380 ; Test a case where the AND comes before a shift right. 381 define i32 @f34(i32 %foo) { 382 ; CHECK-LABEL: f34: 383 ; CHECK: risbg %r2, %r2, 57, 191, 55 384 ; CHECK: br %r14 385 %and = and i32 %foo, 65535 386 %shl = lshr i32 %and, 9 387 ret i32 %shl 388 } 389 390 ; ...and again with i64. 391 define i64 @f35(i64 %foo) { 392 ; CHECK-LABEL: f35: 393 ; CHECK: risbg %r2, %r2, 57, 191, 55 394 ; CHECK: br %r14 395 %and = and i64 %foo, 65535 396 %shl = lshr i64 %and, 9 397 ret i64 %shl 398 } 399 400 ; Test a wrap-around case where the AND comes before a shift right. 401 ; We can't use RISBG for the shift in that case. 402 define i32 @f36(i32 %foo) { 403 ; CHECK-LABEL: f36: 404 ; CHECK: srl %r2 405 ; CHECK: br %r14 406 %and = and i32 %foo, -25 407 %shl = lshr i32 %and, 1 408 ret i32 %shl 409 } 410 411 ; ...and again with i64. 412 define i64 @f37(i64 %foo) { 413 ; CHECK-LABEL: f37: 414 ; CHECK: srlg %r2 415 ; CHECK: br %r14 416 %and = and i64 %foo, -25 417 %shl = lshr i64 %and, 1 418 ret i64 %shl 419 } 420 421 ; Test a combination involving a large ASHR and a shift left. We can't 422 ; use RISBG there. 423 define i64 @f38(i64 %foo) { 424 ; CHECK-LABEL: f38: 425 ; CHECK: srag {{%r[0-5]}} 426 ; CHECK: sllg {{%r[0-5]}} 427 ; CHECK: br %r14 428 %ashr = ashr i64 %foo, 32 429 %shl = shl i64 %ashr, 5 430 ret i64 %shl 431 } 432 433 ; Try a similar thing in which no shifted sign bits are kept. 434 define i64 @f39(i64 %foo, i64 *%dest) { 435 ; CHECK-LABEL: f39: 436 ; CHECK: srag [[REG:%r[01345]]], %r2, 35 437 ; CHECK: risbg %r2, %r2, 33, 189, 31 438 ; CHECK: br %r14 439 %ashr = ashr i64 %foo, 35 440 store i64 %ashr, i64 *%dest 441 %shl = shl i64 %ashr, 2 442 %and = and i64 %shl, 2147483647 443 ret i64 %and 444 } 445 446 ; ...and again with the next highest shift value, where one sign bit is kept. 447 define i64 @f40(i64 %foo, i64 *%dest) { 448 ; CHECK-LABEL: f40: 449 ; CHECK: srag [[REG:%r[01345]]], %r2, 36 450 ; CHECK: risbg %r2, [[REG]], 33, 189, 2 451 ; CHECK: br %r14 452 %ashr = ashr i64 %foo, 36 453 store i64 %ashr, i64 *%dest 454 %shl = shl i64 %ashr, 2 455 %and = and i64 %shl, 2147483647 456 ret i64 %and 457 } 458 459 ; Check a case where the result is zero-extended. 460 define i64 @f41(i32 %a) { 461 ; CHECK-LABEL: f41 462 ; CHECK: risbg %r2, %r2, 36, 191, 62 463 ; CHECK: br %r14 464 %shl = shl i32 %a, 2 465 %shr = lshr i32 %shl, 4 466 %ext = zext i32 %shr to i64 467 ret i64 %ext 468 } 469 470 ; In this case the sign extension is converted to a pair of 32-bit shifts, 471 ; which is then extended to 64 bits. We previously used the wrong bit size 472 ; when testing whether the shifted-in bits of the shift right were significant. 473 define i64 @f42(i1 %x) { 474 ; CHECK-LABEL: f42: 475 ; CHECK: sll %r2, 31 476 ; CHECK: sra %r2, 31 477 ; CHECK: llgcr %r2, %r2 478 ; CHECK: br %r14 479 %ext = sext i1 %x to i8 480 %ext2 = zext i8 %ext to i64 481 ret i64 %ext2 482 } 483 484 ; Check that we get the case where a 64-bit shift is used by a 32-bit and. 485 define signext i32 @f43(i64 %x) { 486 ; CHECK-LABEL: f43: 487 ; CHECK: risbg [[REG:%r[0-5]]], %r2, 32, 189, 52 488 ; CHECK: lgfr %r2, [[REG]] 489 %shr3 = lshr i64 %x, 12 490 %shr3.tr = trunc i64 %shr3 to i32 491 %conv = and i32 %shr3.tr, -4 492 ret i32 %conv 493 } 494 495 ; Check that we don't get the case where the 32-bit and mask is not contiguous 496 define signext i32 @f44(i64 %x) { 497 ; CHECK-LABEL: f44: 498 ; CHECK: srlg [[REG:%r[0-5]]], %r2, 12 499 %shr4 = lshr i64 %x, 12 500 %conv = trunc i64 %shr4 to i32 501 %and = and i32 %conv, 10 502 ret i32 %and 503 } 504
