1 ; Test f64 and v2f64 comparisons. 2 ; 3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 4 5 ; Test oeq. 6 define <2 x i64> @f1(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { 7 ; CHECK-LABEL: f1: 8 ; CHECK: vfcedb %v24, %v26, %v28 9 ; CHECK-NEXT: br %r14 10 %cmp = fcmp oeq <2 x double> %val1, %val2 11 %ret = sext <2 x i1> %cmp to <2 x i64> 12 ret <2 x i64> %ret 13 } 14 15 ; Test one. 16 define <2 x i64> @f2(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { 17 ; CHECK-LABEL: f2: 18 ; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26 19 ; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v26, %v28 20 ; CHECK: vo %v24, [[REG1]], [[REG2]] 21 ; CHECK-NEXT: br %r14 22 %cmp = fcmp one <2 x double> %val1, %val2 23 %ret = sext <2 x i1> %cmp to <2 x i64> 24 ret <2 x i64> %ret 25 } 26 27 ; Test ogt. 28 define <2 x i64> @f3(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { 29 ; CHECK-LABEL: f3: 30 ; CHECK: vfchdb %v24, %v26, %v28 31 ; CHECK-NEXT: br %r14 32 %cmp = fcmp ogt <2 x double> %val1, %val2 33 %ret = sext <2 x i1> %cmp to <2 x i64> 34 ret <2 x i64> %ret 35 } 36 37 ; Test oge. 38 define <2 x i64> @f4(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { 39 ; CHECK-LABEL: f4: 40 ; CHECK: vfchedb %v24, %v26, %v28 41 ; CHECK-NEXT: br %r14 42 %cmp = fcmp oge <2 x double> %val1, %val2 43 %ret = sext <2 x i1> %cmp to <2 x i64> 44 ret <2 x i64> %ret 45 } 46 47 ; Test ole. 48 define <2 x i64> @f5(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { 49 ; CHECK-LABEL: f5: 50 ; CHECK: vfchedb %v24, %v28, %v26 51 ; CHECK-NEXT: br %r14 52 %cmp = fcmp ole <2 x double> %val1, %val2 53 %ret = sext <2 x i1> %cmp to <2 x i64> 54 ret <2 x i64> %ret 55 } 56 57 ; Test olt. 58 define <2 x i64> @f6(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { 59 ; CHECK-LABEL: f6: 60 ; CHECK: vfchdb %v24, %v28, %v26 61 ; CHECK-NEXT: br %r14 62 %cmp = fcmp olt <2 x double> %val1, %val2 63 %ret = sext <2 x i1> %cmp to <2 x i64> 64 ret <2 x i64> %ret 65 } 66 67 ; Test ueq. 68 define <2 x i64> @f7(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { 69 ; CHECK-LABEL: f7: 70 ; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26 71 ; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v26, %v28 72 ; CHECK: vno %v24, [[REG1]], [[REG2]] 73 ; CHECK-NEXT: br %r14 74 %cmp = fcmp ueq <2 x double> %val1, %val2 75 %ret = sext <2 x i1> %cmp to <2 x i64> 76 ret <2 x i64> %ret 77 } 78 79 ; Test une. 80 define <2 x i64> @f8(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { 81 ; CHECK-LABEL: f8: 82 ; CHECK: vfcedb [[REG:%v[0-9]+]], %v26, %v28 83 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]] 84 ; CHECK-NEXT: br %r14 85 %cmp = fcmp une <2 x double> %val1, %val2 86 %ret = sext <2 x i1> %cmp to <2 x i64> 87 ret <2 x i64> %ret 88 } 89 90 ; Test ugt. 91 define <2 x i64> @f9(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { 92 ; CHECK-LABEL: f9: 93 ; CHECK: vfchedb [[REG:%v[0-9]+]], %v28, %v26 94 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]] 95 ; CHECK-NEXT: br %r14 96 %cmp = fcmp ugt <2 x double> %val1, %val2 97 %ret = sext <2 x i1> %cmp to <2 x i64> 98 ret <2 x i64> %ret 99 } 100 101 ; Test uge. 102 define <2 x i64> @f10(<2 x i64> %dummy, <2 x double> %val1, 103 <2 x double> %val2) { 104 ; CHECK-LABEL: f10: 105 ; CHECK: vfchdb [[REG:%v[0-9]+]], %v28, %v26 106 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]] 107 ; CHECK-NEXT: br %r14 108 %cmp = fcmp uge <2 x double> %val1, %val2 109 %ret = sext <2 x i1> %cmp to <2 x i64> 110 ret <2 x i64> %ret 111 } 112 113 ; Test ule. 114 define <2 x i64> @f11(<2 x i64> %dummy, <2 x double> %val1, 115 <2 x double> %val2) { 116 ; CHECK-LABEL: f11: 117 ; CHECK: vfchdb [[REG:%v[0-9]+]], %v26, %v28 118 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]] 119 ; CHECK-NEXT: br %r14 120 %cmp = fcmp ule <2 x double> %val1, %val2 121 %ret = sext <2 x i1> %cmp to <2 x i64> 122 ret <2 x i64> %ret 123 } 124 125 ; Test ult. 126 define <2 x i64> @f12(<2 x i64> %dummy, <2 x double> %val1, 127 <2 x double> %val2) { 128 ; CHECK-LABEL: f12: 129 ; CHECK: vfchedb [[REG:%v[0-9]+]], %v26, %v28 130 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]] 131 ; CHECK-NEXT: br %r14 132 %cmp = fcmp ult <2 x double> %val1, %val2 133 %ret = sext <2 x i1> %cmp to <2 x i64> 134 ret <2 x i64> %ret 135 } 136 137 ; Test ord. 138 define <2 x i64> @f13(<2 x i64> %dummy, <2 x double> %val1, 139 <2 x double> %val2) { 140 ; CHECK-LABEL: f13: 141 ; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26 142 ; CHECK-DAG: vfchedb [[REG2:%v[0-9]+]], %v26, %v28 143 ; CHECK: vo %v24, [[REG1]], [[REG2]] 144 ; CHECK-NEXT: br %r14 145 %cmp = fcmp ord <2 x double> %val1, %val2 146 %ret = sext <2 x i1> %cmp to <2 x i64> 147 ret <2 x i64> %ret 148 } 149 150 ; Test uno. 151 define <2 x i64> @f14(<2 x i64> %dummy, <2 x double> %val1, 152 <2 x double> %val2) { 153 ; CHECK-LABEL: f14: 154 ; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26 155 ; CHECK-DAG: vfchedb [[REG2:%v[0-9]+]], %v26, %v28 156 ; CHECK: vno %v24, [[REG1]], [[REG2]] 157 ; CHECK-NEXT: br %r14 158 %cmp = fcmp uno <2 x double> %val1, %val2 159 %ret = sext <2 x i1> %cmp to <2 x i64> 160 ret <2 x i64> %ret 161 } 162 163 ; Test oeq selects. 164 define <2 x double> @f15(<2 x double> %val1, <2 x double> %val2, 165 <2 x double> %val3, <2 x double> %val4) { 166 ; CHECK-LABEL: f15: 167 ; CHECK: vfcedb [[REG:%v[0-9]+]], %v24, %v26 168 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 169 ; CHECK-NEXT: br %r14 170 %cmp = fcmp oeq <2 x double> %val1, %val2 171 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 172 ret <2 x double> %ret 173 } 174 175 ; Test one selects. 176 define <2 x double> @f16(<2 x double> %val1, <2 x double> %val2, 177 <2 x double> %val3, <2 x double> %val4) { 178 ; CHECK-LABEL: f16: 179 ; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v26, %v24 180 ; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v24, %v26 181 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]] 182 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 183 ; CHECK-NEXT: br %r14 184 %cmp = fcmp one <2 x double> %val1, %val2 185 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 186 ret <2 x double> %ret 187 } 188 189 ; Test ogt selects. 190 define <2 x double> @f17(<2 x double> %val1, <2 x double> %val2, 191 <2 x double> %val3, <2 x double> %val4) { 192 ; CHECK-LABEL: f17: 193 ; CHECK: vfchdb [[REG:%v[0-9]+]], %v24, %v26 194 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 195 ; CHECK-NEXT: br %r14 196 %cmp = fcmp ogt <2 x double> %val1, %val2 197 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 198 ret <2 x double> %ret 199 } 200 201 ; Test oge selects. 202 define <2 x double> @f18(<2 x double> %val1, <2 x double> %val2, 203 <2 x double> %val3, <2 x double> %val4) { 204 ; CHECK-LABEL: f18: 205 ; CHECK: vfchedb [[REG:%v[0-9]+]], %v24, %v26 206 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 207 ; CHECK-NEXT: br %r14 208 %cmp = fcmp oge <2 x double> %val1, %val2 209 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 210 ret <2 x double> %ret 211 } 212 213 ; Test ole selects. 214 define <2 x double> @f19(<2 x double> %val1, <2 x double> %val2, 215 <2 x double> %val3, <2 x double> %val4) { 216 ; CHECK-LABEL: f19: 217 ; CHECK: vfchedb [[REG:%v[0-9]+]], %v26, %v24 218 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 219 ; CHECK-NEXT: br %r14 220 %cmp = fcmp ole <2 x double> %val1, %val2 221 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 222 ret <2 x double> %ret 223 } 224 225 ; Test olt selects. 226 define <2 x double> @f20(<2 x double> %val1, <2 x double> %val2, 227 <2 x double> %val3, <2 x double> %val4) { 228 ; CHECK-LABEL: f20: 229 ; CHECK: vfchdb [[REG:%v[0-9]+]], %v26, %v24 230 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 231 ; CHECK-NEXT: br %r14 232 %cmp = fcmp olt <2 x double> %val1, %val2 233 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 234 ret <2 x double> %ret 235 } 236 237 ; Test ueq selects. 238 define <2 x double> @f21(<2 x double> %val1, <2 x double> %val2, 239 <2 x double> %val3, <2 x double> %val4) { 240 ; CHECK-LABEL: f21: 241 ; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v26, %v24 242 ; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v24, %v26 243 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]] 244 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 245 ; CHECK-NEXT: br %r14 246 %cmp = fcmp ueq <2 x double> %val1, %val2 247 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 248 ret <2 x double> %ret 249 } 250 251 ; Test une selects. 252 define <2 x double> @f22(<2 x double> %val1, <2 x double> %val2, 253 <2 x double> %val3, <2 x double> %val4) { 254 ; CHECK-LABEL: f22: 255 ; CHECK: vfcedb [[REG:%v[0-9]+]], %v24, %v26 256 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 257 ; CHECK-NEXT: br %r14 258 %cmp = fcmp une <2 x double> %val1, %val2 259 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 260 ret <2 x double> %ret 261 } 262 263 ; Test ugt selects. 264 define <2 x double> @f23(<2 x double> %val1, <2 x double> %val2, 265 <2 x double> %val3, <2 x double> %val4) { 266 ; CHECK-LABEL: f23: 267 ; CHECK: vfchedb [[REG:%v[0-9]+]], %v26, %v24 268 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 269 ; CHECK-NEXT: br %r14 270 %cmp = fcmp ugt <2 x double> %val1, %val2 271 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 272 ret <2 x double> %ret 273 } 274 275 ; Test uge selects. 276 define <2 x double> @f24(<2 x double> %val1, <2 x double> %val2, 277 <2 x double> %val3, <2 x double> %val4) { 278 ; CHECK-LABEL: f24: 279 ; CHECK: vfchdb [[REG:%v[0-9]+]], %v26, %v24 280 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 281 ; CHECK-NEXT: br %r14 282 %cmp = fcmp uge <2 x double> %val1, %val2 283 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 284 ret <2 x double> %ret 285 } 286 287 ; Test ule selects. 288 define <2 x double> @f25(<2 x double> %val1, <2 x double> %val2, 289 <2 x double> %val3, <2 x double> %val4) { 290 ; CHECK-LABEL: f25: 291 ; CHECK: vfchdb [[REG:%v[0-9]+]], %v24, %v26 292 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 293 ; CHECK-NEXT: br %r14 294 %cmp = fcmp ule <2 x double> %val1, %val2 295 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 296 ret <2 x double> %ret 297 } 298 299 ; Test ult selects. 300 define <2 x double> @f26(<2 x double> %val1, <2 x double> %val2, 301 <2 x double> %val3, <2 x double> %val4) { 302 ; CHECK-LABEL: f26: 303 ; CHECK: vfchedb [[REG:%v[0-9]+]], %v24, %v26 304 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 305 ; CHECK-NEXT: br %r14 306 %cmp = fcmp ult <2 x double> %val1, %val2 307 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 308 ret <2 x double> %ret 309 } 310 311 ; Test ord selects. 312 define <2 x double> @f27(<2 x double> %val1, <2 x double> %val2, 313 <2 x double> %val3, <2 x double> %val4) { 314 ; CHECK-LABEL: f27: 315 ; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v26, %v24 316 ; CHECK-DAG: vfchedb [[REG2:%v[0-9]+]], %v24, %v26 317 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]] 318 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 319 ; CHECK-NEXT: br %r14 320 %cmp = fcmp ord <2 x double> %val1, %val2 321 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 322 ret <2 x double> %ret 323 } 324 325 ; Test uno selects. 326 define <2 x double> @f28(<2 x double> %val1, <2 x double> %val2, 327 <2 x double> %val3, <2 x double> %val4) { 328 ; CHECK-LABEL: f28: 329 ; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v26, %v24 330 ; CHECK-DAG: vfchedb [[REG2:%v[0-9]+]], %v24, %v26 331 ; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]] 332 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 333 ; CHECK-NEXT: br %r14 334 %cmp = fcmp uno <2 x double> %val1, %val2 335 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 336 ret <2 x double> %ret 337 } 338 339 ; Test an f64 comparison that uses vector registers. 340 define i64 @f29(i64 %a, i64 %b, double %f1, <2 x double> %vec) { 341 ; CHECK-LABEL: f29: 342 ; CHECK: wfcdb %f0, %v24 343 ; CHECK-NEXT: locgrne %r2, %r3 344 ; CHECK: br %r14 345 %f2 = extractelement <2 x double> %vec, i32 0 346 %cond = fcmp oeq double %f1, %f2 347 %res = select i1 %cond, i64 %a, i64 %b 348 ret i64 %res 349 } 350
