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      1 ; RUN: llc -march=x86 -mcpu=i486 -o - %s | FileCheck %s
      2 
      3 ; Main test here was that ISelDAG could cope with a MachineNode in the chain
      4 ; from the first load to the "X86ISD::SUB". Previously it thought that meant no
      5 ; cycle could be formed so it tried to use "sub (%eax), [[RHS]]".
      6 
      7 define void @gst_atomic_queue_push(i32* %addr) {
      8 ; CHECK-LABEL: gst_atomic_queue_push:
      9 ; CHECK: movl (%eax), [[LHS:%e[a-z]+]]
     10 ; CHECK: lock orl
     11 ; CHECK: movl (%eax), [[RHS:%e[a-z]+]]
     12 ; CHECK: cmpl [[LHS]], [[RHS]]
     13 
     14 entry:
     15   br label %while.body
     16 
     17 while.body:
     18   %0 = load volatile i32, i32* %addr, align 4
     19   fence seq_cst
     20   %1 = load volatile i32, i32* %addr, align 4
     21   %cmp = icmp sgt i32 %1, %0
     22   br i1 %cmp, label %while.body, label %if.then
     23 
     24 if.then:
     25   ret void
     26 }