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      1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
      2 ; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx | FileCheck %s
      3 
      4 define <4 x i3> @test1(<4 x i3>* %in) nounwind {
      5 ; CHECK-LABEL: test1:
      6 ; CHECK:       # BB#0:
      7 ; CHECK-NEXT:    movzwl (%rdi), %eax
      8 ; CHECK-NEXT:    movl %eax, %ecx
      9 ; CHECK-NEXT:    shrl $3, %ecx
     10 ; CHECK-NEXT:    vmovd %eax, %xmm0
     11 ; CHECK-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
     12 ; CHECK-NEXT:    movl %eax, %ecx
     13 ; CHECK-NEXT:    shrl $6, %ecx
     14 ; CHECK-NEXT:    vpinsrd $2, %ecx, %xmm0, %xmm0
     15 ; CHECK-NEXT:    shrl $9, %eax
     16 ; CHECK-NEXT:    vpinsrd $3, %eax, %xmm0, %xmm0
     17 ; CHECK-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
     18 ; CHECK-NEXT:    retq
     19   %ret = load <4 x i3>, <4 x i3>* %in, align 1
     20   ret <4 x i3> %ret
     21 }
     22 
     23 define <4 x i1> @test2(<4 x i1>* %in) nounwind {
     24 ; CHECK-LABEL: test2:
     25 ; CHECK:       # BB#0:
     26 ; CHECK-NEXT:    movzbl (%rdi), %eax
     27 ; CHECK-NEXT:    movl %eax, %ecx
     28 ; CHECK-NEXT:    shrl %ecx
     29 ; CHECK-NEXT:    vmovd %eax, %xmm0
     30 ; CHECK-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
     31 ; CHECK-NEXT:    movl %eax, %ecx
     32 ; CHECK-NEXT:    shrl $2, %ecx
     33 ; CHECK-NEXT:    vpinsrd $2, %ecx, %xmm0, %xmm0
     34 ; CHECK-NEXT:    shrl $3, %eax
     35 ; CHECK-NEXT:    vpinsrd $3, %eax, %xmm0, %xmm0
     36 ; CHECK-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
     37 ; CHECK-NEXT:    retq
     38   %ret = load <4 x i1>, <4 x i1>* %in, align 1
     39   ret <4 x i1> %ret
     40 }
     41 
     42 define <4 x i64> @test3(<4 x i1>* %in) nounwind {
     43 ; CHECK-LABEL: test3:
     44 ; CHECK:       # BB#0:
     45 ; CHECK-NEXT:    movzbl (%rdi), %eax
     46 ; CHECK-NEXT:    movq %rax, %rcx
     47 ; CHECK-NEXT:    shlq $62, %rcx
     48 ; CHECK-NEXT:    sarq $63, %rcx
     49 ; CHECK-NEXT:    movq %rax, %rdx
     50 ; CHECK-NEXT:    shlq $63, %rdx
     51 ; CHECK-NEXT:    sarq $63, %rdx
     52 ; CHECK-NEXT:    vmovd %edx, %xmm0
     53 ; CHECK-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
     54 ; CHECK-NEXT:    movq %rax, %rcx
     55 ; CHECK-NEXT:    shlq $61, %rcx
     56 ; CHECK-NEXT:    sarq $63, %rcx
     57 ; CHECK-NEXT:    vpinsrd $2, %ecx, %xmm0, %xmm0
     58 ; CHECK-NEXT:    shlq $60, %rax
     59 ; CHECK-NEXT:    sarq $63, %rax
     60 ; CHECK-NEXT:    vpinsrd $3, %eax, %xmm0, %xmm0
     61 ; CHECK-NEXT:    vpmovsxdq %xmm0, %xmm1
     62 ; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
     63 ; CHECK-NEXT:    vpmovsxdq %xmm0, %xmm0
     64 ; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
     65 ; CHECK-NEXT:    retq
     66   %wide.load35 = load <4 x i1>, <4 x i1>* %in, align 1
     67   %sext = sext <4 x i1> %wide.load35 to <4 x i64>
     68   ret <4 x i64> %sext
     69 }
     70 
     71 define <16 x i4> @test4(<16 x i4>* %in) nounwind {
     72 ; CHECK-LABEL: test4:
     73 ; CHECK:       # BB#0:
     74 ; CHECK-NEXT:    movq (%rdi), %rax
     75 ; CHECK-NEXT:    movl %eax, %ecx
     76 ; CHECK-NEXT:    shrl $4, %ecx
     77 ; CHECK-NEXT:    andl $15, %ecx
     78 ; CHECK-NEXT:    movl %eax, %edx
     79 ; CHECK-NEXT:    andl $15, %edx
     80 ; CHECK-NEXT:    vmovd %edx, %xmm0
     81 ; CHECK-NEXT:    vpinsrb $1, %ecx, %xmm0, %xmm0
     82 ; CHECK-NEXT:    movl %eax, %ecx
     83 ; CHECK-NEXT:    shrl $8, %ecx
     84 ; CHECK-NEXT:    andl $15, %ecx
     85 ; CHECK-NEXT:    vpinsrb $2, %ecx, %xmm0, %xmm0
     86 ; CHECK-NEXT:    movl %eax, %ecx
     87 ; CHECK-NEXT:    shrl $12, %ecx
     88 ; CHECK-NEXT:    andl $15, %ecx
     89 ; CHECK-NEXT:    vpinsrb $3, %ecx, %xmm0, %xmm0
     90 ; CHECK-NEXT:    movl %eax, %ecx
     91 ; CHECK-NEXT:    shrl $16, %ecx
     92 ; CHECK-NEXT:    andl $15, %ecx
     93 ; CHECK-NEXT:    vpinsrb $4, %ecx, %xmm0, %xmm0
     94 ; CHECK-NEXT:    movl %eax, %ecx
     95 ; CHECK-NEXT:    shrl $20, %ecx
     96 ; CHECK-NEXT:    andl $15, %ecx
     97 ; CHECK-NEXT:    vpinsrb $5, %ecx, %xmm0, %xmm0
     98 ; CHECK-NEXT:    movl %eax, %ecx
     99 ; CHECK-NEXT:    shrl $24, %ecx
    100 ; CHECK-NEXT:    andl $15, %ecx
    101 ; CHECK-NEXT:    vpinsrb $6, %ecx, %xmm0, %xmm0
    102 ; CHECK-NEXT:    movl %eax, %ecx
    103 ; CHECK-NEXT:    shrl $28, %ecx
    104 ; CHECK-NEXT:    vpinsrb $7, %ecx, %xmm0, %xmm0
    105 ; CHECK-NEXT:    movq %rax, %rcx
    106 ; CHECK-NEXT:    shrq $32, %rcx
    107 ; CHECK-NEXT:    andl $15, %ecx
    108 ; CHECK-NEXT:    vpinsrb $8, %ecx, %xmm0, %xmm0
    109 ; CHECK-NEXT:    movq %rax, %rcx
    110 ; CHECK-NEXT:    shrq $36, %rcx
    111 ; CHECK-NEXT:    andl $15, %ecx
    112 ; CHECK-NEXT:    vpinsrb $9, %ecx, %xmm0, %xmm0
    113 ; CHECK-NEXT:    movq %rax, %rcx
    114 ; CHECK-NEXT:    shrq $40, %rcx
    115 ; CHECK-NEXT:    andl $15, %ecx
    116 ; CHECK-NEXT:    vpinsrb $10, %ecx, %xmm0, %xmm0
    117 ; CHECK-NEXT:    movq %rax, %rcx
    118 ; CHECK-NEXT:    shrq $44, %rcx
    119 ; CHECK-NEXT:    andl $15, %ecx
    120 ; CHECK-NEXT:    vpinsrb $11, %ecx, %xmm0, %xmm0
    121 ; CHECK-NEXT:    movq %rax, %rcx
    122 ; CHECK-NEXT:    shrq $48, %rcx
    123 ; CHECK-NEXT:    andl $15, %ecx
    124 ; CHECK-NEXT:    vpinsrb $12, %ecx, %xmm0, %xmm0
    125 ; CHECK-NEXT:    movq %rax, %rcx
    126 ; CHECK-NEXT:    shrq $52, %rcx
    127 ; CHECK-NEXT:    andl $15, %ecx
    128 ; CHECK-NEXT:    vpinsrb $13, %ecx, %xmm0, %xmm0
    129 ; CHECK-NEXT:    movq %rax, %rcx
    130 ; CHECK-NEXT:    shrq $56, %rcx
    131 ; CHECK-NEXT:    andl $15, %ecx
    132 ; CHECK-NEXT:    vpinsrb $14, %ecx, %xmm0, %xmm0
    133 ; CHECK-NEXT:    shrq $60, %rax
    134 ; CHECK-NEXT:    vpinsrb $15, %eax, %xmm0, %xmm0
    135 ; CHECK-NEXT:    retq
    136   %ret = load <16 x i4>, <16 x i4>* %in, align 1
    137   ret <16 x i4> %ret
    138 }
    139