1 ; RUN: llc < %s -O1 -mtriple=i386-apple-darwin -x86-asm-syntax=intel | FileCheck %s 2 ; 3 ; Interesting test case where %tmp1220 = xor i32 %tmp862, %tmp592 and 4 ; %tmp1676 = xor i32 %tmp1634, %tmp1530 have zero demanded bits after 5 ; DAGCombiner optimization pass. These are changed to undef and in turn 6 ; the successor shl(s) become shl undef, 1. This pattern then matches 7 ; shl x, 1 -> add x, x. add undef, undef doesn't guarantee the low 8 ; order bit is zero and is incorrect. 9 ; 10 ; See rdar://9453156 and rdar://9487392. 11 ; 12 13 ; Use intel syntax, or "shl" might hit "pushl". 14 15 ; CHECK-NOT: shl 16 define i32 @foo(i8* %a0, i32* %a2) nounwind { 17 entry: 18 %tmp0 = alloca i8 19 %tmp1 = alloca i32 20 store i8 1, i8* %tmp0 21 %tmp921.i7845 = load i8, i8* %a0, align 1 22 %tmp309 = xor i8 %tmp921.i7845, 104 23 %tmp592 = zext i8 %tmp309 to i32 24 %tmp862 = xor i32 1293461297, %tmp592 25 %tmp1220 = xor i32 %tmp862, %tmp592 26 %tmp1506 = shl i32 %tmp1220, 1 27 %tmp1530 = sub i32 %tmp592, %tmp1506 28 %tmp1557 = sub i32 %tmp1530, 542767629 29 %tmp1607 = and i32 %tmp1557, 1 30 store i32 %tmp1607, i32* %tmp1 31 %tmp1634 = and i32 %tmp1607, 2080309246 32 %tmp1676 = xor i32 %tmp1634, %tmp1530 33 %tmp1618 = shl i32 %tmp1676, 1 34 %tmp1645 = sub i32 %tmp862, %tmp1618 35 %tmp1697 = and i32 %tmp1645, 1 36 store i32 %tmp1697, i32* %a2 37 ret i32 %tmp1607 38 } 39 40 ; CHECK-NOT: shl 41 ; shl undef, 0 -> undef 42 define i32 @foo2_undef() nounwind { 43 entry: 44 %tmp2 = shl i32 undef, 0; 45 ret i32 %tmp2 46 } 47 48 ; CHECK-NOT: shl 49 ; shl undef, x -> 0 50 define i32 @foo1_undef(i32* %a0) nounwind { 51 entry: 52 %tmp1 = load i32, i32* %a0, align 1 53 %tmp2 = shl i32 undef, %tmp1; 54 ret i32 %tmp2 55 } 56
