1 /************************************************************************** 2 * 3 * Copyright 2008 VMware, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #include "util/u_debug.h" 29 #include "util/u_memory.h" 30 #include "tgsi_info.h" 31 32 #define NONE TGSI_OUTPUT_NONE 33 #define COMP TGSI_OUTPUT_COMPONENTWISE 34 #define REPL TGSI_OUTPUT_REPLICATE 35 #define CHAN TGSI_OUTPUT_CHAN_DEPENDENT 36 #define OTHR TGSI_OUTPUT_OTHER 37 38 static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] = 39 { 40 { 1, 1, 0, 0, 0, 0, 0, COMP, "ARL", TGSI_OPCODE_ARL }, 41 { 1, 1, 0, 0, 0, 0, 0, COMP, "MOV", TGSI_OPCODE_MOV }, 42 { 1, 1, 0, 0, 0, 0, 0, CHAN, "LIT", TGSI_OPCODE_LIT }, 43 { 1, 1, 0, 0, 0, 0, 0, REPL, "RCP", TGSI_OPCODE_RCP }, 44 { 1, 1, 0, 0, 0, 0, 0, REPL, "RSQ", TGSI_OPCODE_RSQ }, 45 { 1, 1, 0, 0, 0, 0, 0, CHAN, "EXP", TGSI_OPCODE_EXP }, 46 { 1, 1, 0, 0, 0, 0, 0, CHAN, "LOG", TGSI_OPCODE_LOG }, 47 { 1, 2, 0, 0, 0, 0, 0, COMP, "MUL", TGSI_OPCODE_MUL }, 48 { 1, 2, 0, 0, 0, 0, 0, COMP, "ADD", TGSI_OPCODE_ADD }, 49 { 1, 2, 0, 0, 0, 0, 0, REPL, "DP3", TGSI_OPCODE_DP3 }, 50 { 1, 2, 0, 0, 0, 0, 0, REPL, "DP4", TGSI_OPCODE_DP4 }, 51 { 1, 2, 0, 0, 0, 0, 0, CHAN, "DST", TGSI_OPCODE_DST }, 52 { 1, 2, 0, 0, 0, 0, 0, COMP, "MIN", TGSI_OPCODE_MIN }, 53 { 1, 2, 0, 0, 0, 0, 0, COMP, "MAX", TGSI_OPCODE_MAX }, 54 { 1, 2, 0, 0, 0, 0, 0, COMP, "SLT", TGSI_OPCODE_SLT }, 55 { 1, 2, 0, 0, 0, 0, 0, COMP, "SGE", TGSI_OPCODE_SGE }, 56 { 1, 3, 0, 0, 0, 0, 0, COMP, "MAD", TGSI_OPCODE_MAD }, 57 { 1, 2, 0, 0, 0, 0, 0, COMP, "", 17 }, /* removed */ 58 { 1, 3, 0, 0, 0, 0, 0, COMP, "LRP", TGSI_OPCODE_LRP }, 59 { 1, 3, 0, 0, 0, 0, 0, COMP, "FMA", TGSI_OPCODE_FMA }, 60 { 1, 1, 0, 0, 0, 0, 0, REPL, "SQRT", TGSI_OPCODE_SQRT }, 61 { 1, 3, 0, 0, 0, 0, 0, REPL, "DP2A", TGSI_OPCODE_DP2A }, 62 { 1, 1, 0, 0, 0, 0, 0, COMP, "F2U64", TGSI_OPCODE_F2U64 }, 63 { 1, 1, 0, 0, 0, 0, 0, COMP, "F2I64", TGSI_OPCODE_F2I64 }, 64 { 1, 1, 0, 0, 0, 0, 0, COMP, "FRC", TGSI_OPCODE_FRC }, 65 { 1, 3, 0, 0, 0, 0, 0, COMP, "CLAMP", TGSI_OPCODE_CLAMP }, 66 { 1, 1, 0, 0, 0, 0, 0, COMP, "FLR", TGSI_OPCODE_FLR }, 67 { 1, 1, 0, 0, 0, 0, 0, COMP, "ROUND", TGSI_OPCODE_ROUND }, 68 { 1, 1, 0, 0, 0, 0, 0, REPL, "EX2", TGSI_OPCODE_EX2 }, 69 { 1, 1, 0, 0, 0, 0, 0, REPL, "LG2", TGSI_OPCODE_LG2 }, 70 { 1, 2, 0, 0, 0, 0, 0, REPL, "POW", TGSI_OPCODE_POW }, 71 { 1, 2, 0, 0, 0, 0, 0, COMP, "XPD", TGSI_OPCODE_XPD }, 72 { 1, 1, 0, 0, 0, 0, 0, COMP, "U2I64", TGSI_OPCODE_U2I64 }, 73 { 1, 1, 0, 0, 0, 0, 0, COMP, "", 33 }, /* removed */ 74 { 1, 1, 0, 0, 0, 0, 0, COMP, "I2I64", TGSI_OPCODE_I2I64 }, 75 { 1, 2, 0, 0, 0, 0, 0, REPL, "DPH", TGSI_OPCODE_DPH }, 76 { 1, 1, 0, 0, 0, 0, 0, REPL, "COS", TGSI_OPCODE_COS }, 77 { 1, 1, 0, 0, 0, 0, 0, COMP, "DDX", TGSI_OPCODE_DDX }, 78 { 1, 1, 0, 0, 0, 0, 0, COMP, "DDY", TGSI_OPCODE_DDY }, 79 { 0, 0, 0, 0, 0, 0, 0, NONE, "KILL", TGSI_OPCODE_KILL }, 80 { 1, 1, 0, 0, 0, 0, 0, REPL, "PK2H", TGSI_OPCODE_PK2H }, 81 { 1, 1, 0, 0, 0, 0, 0, REPL, "PK2US", TGSI_OPCODE_PK2US }, 82 { 1, 1, 0, 0, 0, 0, 0, REPL, "PK4B", TGSI_OPCODE_PK4B }, 83 { 1, 1, 0, 0, 0, 0, 0, REPL, "PK4UB", TGSI_OPCODE_PK4UB }, 84 { 1, 1, 0, 0, 0, 0, 1, COMP, "D2U64", TGSI_OPCODE_D2U64 }, 85 { 1, 2, 0, 0, 0, 0, 0, COMP, "SEQ", TGSI_OPCODE_SEQ }, 86 { 1, 1, 0, 0, 0, 0, 1, COMP, "D2I64", TGSI_OPCODE_D2I64 }, 87 { 1, 2, 0, 0, 0, 0, 0, COMP, "SGT", TGSI_OPCODE_SGT }, 88 { 1, 1, 0, 0, 0, 0, 0, REPL, "SIN", TGSI_OPCODE_SIN }, 89 { 1, 2, 0, 0, 0, 0, 0, COMP, "SLE", TGSI_OPCODE_SLE }, 90 { 1, 2, 0, 0, 0, 0, 0, COMP, "SNE", TGSI_OPCODE_SNE }, 91 { 1, 1, 0, 0, 0, 0, 1, COMP, "U642D", TGSI_OPCODE_U642D }, 92 { 1, 2, 1, 0, 0, 0, 0, OTHR, "TEX", TGSI_OPCODE_TEX }, 93 { 1, 4, 1, 0, 0, 0, 0, OTHR, "TXD", TGSI_OPCODE_TXD }, 94 { 1, 2, 1, 0, 0, 0, 0, OTHR, "TXP", TGSI_OPCODE_TXP }, 95 { 1, 1, 0, 0, 0, 0, 0, CHAN, "UP2H", TGSI_OPCODE_UP2H }, 96 { 1, 1, 0, 0, 0, 0, 0, CHAN, "UP2US", TGSI_OPCODE_UP2US }, 97 { 1, 1, 0, 0, 0, 0, 0, CHAN, "UP4B", TGSI_OPCODE_UP4B }, 98 { 1, 1, 0, 0, 0, 0, 0, CHAN, "UP4UB", TGSI_OPCODE_UP4UB }, 99 { 1, 1, 0, 0, 0, 0, 1, COMP, "U642F", TGSI_OPCODE_U642F }, 100 { 1, 1, 0, 0, 0, 0, 1, COMP, "I642F", TGSI_OPCODE_I642F }, 101 { 1, 1, 0, 0, 0, 0, 0, COMP, "ARR", TGSI_OPCODE_ARR }, 102 { 1, 1, 0, 0, 0, 0, 1, COMP, "I642D", TGSI_OPCODE_I642D }, 103 { 0, 0, 0, 0, 1, 0, 0, NONE, "CAL", TGSI_OPCODE_CAL }, 104 { 0, 0, 0, 0, 0, 0, 0, NONE, "RET", TGSI_OPCODE_RET }, 105 { 1, 1, 0, 0, 0, 0, 0, COMP, "SSG", TGSI_OPCODE_SSG }, 106 { 1, 3, 0, 0, 0, 0, 0, COMP, "CMP", TGSI_OPCODE_CMP }, 107 { 1, 1, 0, 0, 0, 0, 0, CHAN, "SCS", TGSI_OPCODE_SCS }, 108 { 1, 2, 1, 0, 0, 0, 0, OTHR, "TXB", TGSI_OPCODE_TXB }, 109 { 1, 1, 0, 0, 0, 0, 0, OTHR, "FBFETCH", TGSI_OPCODE_FBFETCH }, 110 { 1, 2, 0, 0, 0, 0, 0, COMP, "DIV", TGSI_OPCODE_DIV }, 111 { 1, 2, 0, 0, 0, 0, 0, REPL, "DP2", TGSI_OPCODE_DP2 }, 112 { 1, 2, 1, 0, 0, 0, 0, OTHR, "TXL", TGSI_OPCODE_TXL }, 113 { 0, 0, 0, 0, 0, 0, 0, NONE, "BRK", TGSI_OPCODE_BRK }, 114 { 0, 1, 0, 0, 1, 0, 1, NONE, "IF", TGSI_OPCODE_IF }, 115 { 0, 1, 0, 0, 1, 0, 1, NONE, "UIF", TGSI_OPCODE_UIF }, 116 { 0, 1, 0, 0, 0, 0, 1, NONE, "", 76 }, /* removed */ 117 { 0, 0, 0, 0, 1, 1, 1, NONE, "ELSE", TGSI_OPCODE_ELSE }, 118 { 0, 0, 0, 0, 0, 1, 0, NONE, "ENDIF", TGSI_OPCODE_ENDIF }, 119 { 1, 1, 0, 0, 0, 0, 0, COMP, "DDX_FINE", TGSI_OPCODE_DDX_FINE }, 120 { 1, 1, 0, 0, 0, 0, 0, COMP, "DDY_FINE", TGSI_OPCODE_DDY_FINE }, 121 { 0, 1, 0, 0, 0, 0, 0, NONE, "PUSHA", TGSI_OPCODE_PUSHA }, 122 { 1, 0, 0, 0, 0, 0, 0, NONE, "POPA", TGSI_OPCODE_POPA }, 123 { 1, 1, 0, 0, 0, 0, 0, COMP, "CEIL", TGSI_OPCODE_CEIL }, 124 { 1, 1, 0, 0, 0, 0, 0, COMP, "I2F", TGSI_OPCODE_I2F }, 125 { 1, 1, 0, 0, 0, 0, 0, COMP, "NOT", TGSI_OPCODE_NOT }, 126 { 1, 1, 0, 0, 0, 0, 0, COMP, "TRUNC", TGSI_OPCODE_TRUNC }, 127 { 1, 2, 0, 0, 0, 0, 0, COMP, "SHL", TGSI_OPCODE_SHL }, 128 { 0, 0, 0, 0, 0, 0, 0, NONE, "", 88 }, /* removed */ 129 { 1, 2, 0, 0, 0, 0, 0, COMP, "AND", TGSI_OPCODE_AND }, 130 { 1, 2, 0, 0, 0, 0, 0, COMP, "OR", TGSI_OPCODE_OR }, 131 { 1, 2, 0, 0, 0, 0, 0, COMP, "MOD", TGSI_OPCODE_MOD }, 132 { 1, 2, 0, 0, 0, 0, 0, COMP, "XOR", TGSI_OPCODE_XOR }, 133 { 1, 3, 0, 0, 0, 0, 0, COMP, "SAD", TGSI_OPCODE_SAD }, 134 { 1, 2, 1, 0, 0, 0, 0, OTHR, "TXF", TGSI_OPCODE_TXF }, 135 { 1, 2, 1, 0, 0, 0, 0, OTHR, "TXQ", TGSI_OPCODE_TXQ }, 136 { 0, 0, 0, 0, 0, 0, 0, NONE, "CONT", TGSI_OPCODE_CONT }, 137 { 0, 1, 0, 0, 0, 0, 0, NONE, "EMIT", TGSI_OPCODE_EMIT }, 138 { 0, 1, 0, 0, 0, 0, 0, NONE, "ENDPRIM", TGSI_OPCODE_ENDPRIM }, 139 { 0, 0, 0, 0, 1, 0, 1, NONE, "BGNLOOP", TGSI_OPCODE_BGNLOOP }, 140 { 0, 0, 0, 0, 0, 0, 1, NONE, "BGNSUB", TGSI_OPCODE_BGNSUB }, 141 { 0, 0, 0, 0, 1, 1, 0, NONE, "ENDLOOP", TGSI_OPCODE_ENDLOOP }, 142 { 0, 0, 0, 0, 0, 1, 0, NONE, "ENDSUB", TGSI_OPCODE_ENDSUB }, 143 { 1, 1, 1, 0, 0, 0, 0, OTHR, "TXQ_LZ", TGSI_OPCODE_TXQ_LZ }, 144 { 1, 1, 1, 0, 0, 0, 0, OTHR, "TXQS", TGSI_OPCODE_TXQS }, 145 { 1, 1, 0, 0, 0, 0, 0, OTHR, "RESQ", TGSI_OPCODE_RESQ }, 146 { 0, 0, 0, 0, 0, 0, 0, NONE, "", 106 }, /* removed */ 147 { 0, 0, 0, 0, 0, 0, 0, NONE, "NOP", TGSI_OPCODE_NOP }, 148 { 1, 2, 0, 0, 0, 0, 0, COMP, "FSEQ", TGSI_OPCODE_FSEQ }, 149 { 1, 2, 0, 0, 0, 0, 0, COMP, "FSGE", TGSI_OPCODE_FSGE }, 150 { 1, 2, 0, 0, 0, 0, 0, COMP, "FSLT", TGSI_OPCODE_FSLT }, 151 { 1, 2, 0, 0, 0, 0, 0, COMP, "FSNE", TGSI_OPCODE_FSNE }, 152 { 0, 1, 0, 0, 0, 0, 0, OTHR, "MEMBAR", TGSI_OPCODE_MEMBAR }, 153 { 0, 1, 0, 0, 0, 0, 0, NONE, "CALLNZ", TGSI_OPCODE_CALLNZ }, 154 { 0, 1, 0, 0, 0, 0, 0, NONE, "", 114 }, /* removed */ 155 { 0, 1, 0, 0, 0, 0, 0, NONE, "BREAKC", TGSI_OPCODE_BREAKC }, 156 { 0, 1, 0, 0, 0, 0, 0, NONE, "KILL_IF", TGSI_OPCODE_KILL_IF }, 157 { 0, 0, 0, 0, 0, 0, 0, NONE, "END", TGSI_OPCODE_END }, 158 { 1, 3, 0, 0, 0, 0, 0, COMP, "DFMA", TGSI_OPCODE_DFMA }, 159 { 1, 1, 0, 0, 0, 0, 0, COMP, "F2I", TGSI_OPCODE_F2I }, 160 { 1, 2, 0, 0, 0, 0, 0, COMP, "IDIV", TGSI_OPCODE_IDIV }, 161 { 1, 2, 0, 0, 0, 0, 0, COMP, "IMAX", TGSI_OPCODE_IMAX }, 162 { 1, 2, 0, 0, 0, 0, 0, COMP, "IMIN", TGSI_OPCODE_IMIN }, 163 { 1, 1, 0, 0, 0, 0, 0, COMP, "INEG", TGSI_OPCODE_INEG }, 164 { 1, 2, 0, 0, 0, 0, 0, COMP, "ISGE", TGSI_OPCODE_ISGE }, 165 { 1, 2, 0, 0, 0, 0, 0, COMP, "ISHR", TGSI_OPCODE_ISHR }, 166 { 1, 2, 0, 0, 0, 0, 0, COMP, "ISLT", TGSI_OPCODE_ISLT }, 167 { 1, 1, 0, 0, 0, 0, 0, COMP, "F2U", TGSI_OPCODE_F2U }, 168 { 1, 1, 0, 0, 0, 0, 0, COMP, "U2F", TGSI_OPCODE_U2F }, 169 { 1, 2, 0, 0, 0, 0, 0, COMP, "UADD", TGSI_OPCODE_UADD }, 170 { 1, 2, 0, 0, 0, 0, 0, COMP, "UDIV", TGSI_OPCODE_UDIV }, 171 { 1, 3, 0, 0, 0, 0, 0, COMP, "UMAD", TGSI_OPCODE_UMAD }, 172 { 1, 2, 0, 0, 0, 0, 0, COMP, "UMAX", TGSI_OPCODE_UMAX }, 173 { 1, 2, 0, 0, 0, 0, 0, COMP, "UMIN", TGSI_OPCODE_UMIN }, 174 { 1, 2, 0, 0, 0, 0, 0, COMP, "UMOD", TGSI_OPCODE_UMOD }, 175 { 1, 2, 0, 0, 0, 0, 0, COMP, "UMUL", TGSI_OPCODE_UMUL }, 176 { 1, 2, 0, 0, 0, 0, 0, COMP, "USEQ", TGSI_OPCODE_USEQ }, 177 { 1, 2, 0, 0, 0, 0, 0, COMP, "USGE", TGSI_OPCODE_USGE }, 178 { 1, 2, 0, 0, 0, 0, 0, COMP, "USHR", TGSI_OPCODE_USHR }, 179 { 1, 2, 0, 0, 0, 0, 0, COMP, "USLT", TGSI_OPCODE_USLT }, 180 { 1, 2, 0, 0, 0, 0, 0, COMP, "USNE", TGSI_OPCODE_USNE }, 181 { 0, 1, 0, 0, 0, 0, 0, NONE, "SWITCH", TGSI_OPCODE_SWITCH }, 182 { 0, 1, 0, 0, 0, 0, 0, NONE, "CASE", TGSI_OPCODE_CASE }, 183 { 0, 0, 0, 0, 0, 0, 0, NONE, "DEFAULT", TGSI_OPCODE_DEFAULT }, 184 { 0, 0, 0, 0, 0, 0, 0, NONE, "ENDSWITCH", TGSI_OPCODE_ENDSWITCH }, 185 186 { 1, 3, 0, 0, 0, 0, 0, OTHR, "SAMPLE", TGSI_OPCODE_SAMPLE }, 187 { 1, 2, 0, 0, 0, 0, 0, OTHR, "SAMPLE_I", TGSI_OPCODE_SAMPLE_I }, 188 { 1, 3, 0, 0, 0, 0, 0, OTHR, "SAMPLE_I_MS", TGSI_OPCODE_SAMPLE_I_MS }, 189 { 1, 4, 0, 0, 0, 0, 0, OTHR, "SAMPLE_B", TGSI_OPCODE_SAMPLE_B }, 190 { 1, 4, 0, 0, 0, 0, 0, OTHR, "SAMPLE_C", TGSI_OPCODE_SAMPLE_C }, 191 { 1, 4, 0, 0, 0, 0, 0, OTHR, "SAMPLE_C_LZ", TGSI_OPCODE_SAMPLE_C_LZ }, 192 { 1, 5, 0, 0, 0, 0, 0, OTHR, "SAMPLE_D", TGSI_OPCODE_SAMPLE_D }, 193 { 1, 4, 0, 0, 0, 0, 0, OTHR, "SAMPLE_L", TGSI_OPCODE_SAMPLE_L }, 194 { 1, 3, 0, 0, 0, 0, 0, OTHR, "GATHER4", TGSI_OPCODE_GATHER4 }, 195 { 1, 2, 0, 0, 0, 0, 0, OTHR, "SVIEWINFO", TGSI_OPCODE_SVIEWINFO }, 196 { 1, 2, 0, 0, 0, 0, 0, OTHR, "SAMPLE_POS", TGSI_OPCODE_SAMPLE_POS }, 197 { 1, 2, 0, 0, 0, 0, 0, OTHR, "SAMPLE_INFO", TGSI_OPCODE_SAMPLE_INFO }, 198 { 1, 1, 0, 0, 0, 0, 0, COMP, "UARL", TGSI_OPCODE_UARL }, 199 { 1, 3, 0, 0, 0, 0, 0, COMP, "UCMP", TGSI_OPCODE_UCMP }, 200 { 1, 1, 0, 0, 0, 0, 0, COMP, "IABS", TGSI_OPCODE_IABS }, 201 { 1, 1, 0, 0, 0, 0, 0, COMP, "ISSG", TGSI_OPCODE_ISSG }, 202 { 1, 2, 0, 0, 0, 0, 0, OTHR, "LOAD", TGSI_OPCODE_LOAD }, 203 { 1, 2, 0, 1, 0, 0, 0, OTHR, "STORE", TGSI_OPCODE_STORE }, 204 { 1, 0, 0, 0, 0, 0, 0, OTHR, "MFENCE", TGSI_OPCODE_MFENCE }, 205 { 1, 0, 0, 0, 0, 0, 0, OTHR, "LFENCE", TGSI_OPCODE_LFENCE }, 206 { 1, 0, 0, 0, 0, 0, 0, OTHR, "SFENCE", TGSI_OPCODE_SFENCE }, 207 { 0, 0, 0, 0, 0, 0, 0, OTHR, "BARRIER", TGSI_OPCODE_BARRIER }, 208 209 { 1, 3, 0, 1, 0, 0, 0, OTHR, "ATOMUADD", TGSI_OPCODE_ATOMUADD }, 210 { 1, 3, 0, 1, 0, 0, 0, OTHR, "ATOMXCHG", TGSI_OPCODE_ATOMXCHG }, 211 { 1, 4, 0, 1, 0, 0, 0, OTHR, "ATOMCAS", TGSI_OPCODE_ATOMCAS }, 212 { 1, 3, 0, 1, 0, 0, 0, OTHR, "ATOMAND", TGSI_OPCODE_ATOMAND }, 213 { 1, 3, 0, 1, 0, 0, 0, OTHR, "ATOMOR", TGSI_OPCODE_ATOMOR }, 214 { 1, 3, 0, 1, 0, 0, 0, OTHR, "ATOMXOR", TGSI_OPCODE_ATOMXOR }, 215 { 1, 3, 0, 1, 0, 0, 0, OTHR, "ATOMUMIN", TGSI_OPCODE_ATOMUMIN }, 216 { 1, 3, 0, 1, 0, 0, 0, OTHR, "ATOMUMAX", TGSI_OPCODE_ATOMUMAX }, 217 { 1, 3, 0, 1, 0, 0, 0, OTHR, "ATOMIMIN", TGSI_OPCODE_ATOMIMIN }, 218 { 1, 3, 0, 1, 0, 0, 0, OTHR, "ATOMIMAX", TGSI_OPCODE_ATOMIMAX }, 219 { 1, 3, 1, 0, 0, 0, 0, OTHR, "TEX2", TGSI_OPCODE_TEX2 }, 220 { 1, 3, 1, 0, 0, 0, 0, OTHR, "TXB2", TGSI_OPCODE_TXB2 }, 221 { 1, 3, 1, 0, 0, 0, 0, OTHR, "TXL2", TGSI_OPCODE_TXL2 }, 222 { 1, 2, 0, 0, 0, 0, 0, COMP, "IMUL_HI", TGSI_OPCODE_IMUL_HI }, 223 { 1, 2, 0, 0, 0, 0, 0, COMP, "UMUL_HI", TGSI_OPCODE_UMUL_HI }, 224 { 1, 3, 1, 0, 0, 0, 0, OTHR, "TG4", TGSI_OPCODE_TG4 }, 225 { 1, 2, 1, 0, 0, 0, 0, OTHR, "LODQ", TGSI_OPCODE_LODQ }, 226 { 1, 3, 0, 0, 0, 0, 0, COMP, "IBFE", TGSI_OPCODE_IBFE }, 227 { 1, 3, 0, 0, 0, 0, 0, COMP, "UBFE", TGSI_OPCODE_UBFE }, 228 { 1, 4, 0, 0, 0, 0, 0, COMP, "BFI", TGSI_OPCODE_BFI }, 229 { 1, 1, 0, 0, 0, 0, 0, COMP, "BREV", TGSI_OPCODE_BREV }, 230 { 1, 1, 0, 0, 0, 0, 0, COMP, "POPC", TGSI_OPCODE_POPC }, 231 { 1, 1, 0, 0, 0, 0, 0, COMP, "LSB", TGSI_OPCODE_LSB }, 232 { 1, 1, 0, 0, 0, 0, 0, COMP, "IMSB", TGSI_OPCODE_IMSB }, 233 { 1, 1, 0, 0, 0, 0, 0, COMP, "UMSB", TGSI_OPCODE_UMSB }, 234 { 1, 1, 0, 0, 0, 0, 0, OTHR, "INTERP_CENTROID", TGSI_OPCODE_INTERP_CENTROID }, 235 { 1, 2, 0, 0, 0, 0, 0, OTHR, "INTERP_SAMPLE", TGSI_OPCODE_INTERP_SAMPLE }, 236 { 1, 2, 0, 0, 0, 0, 0, OTHR, "INTERP_OFFSET", TGSI_OPCODE_INTERP_OFFSET }, 237 { 1, 1, 0, 0, 0, 0, 0, COMP, "F2D", TGSI_OPCODE_F2D }, 238 { 1, 1, 0, 0, 0, 0, 0, COMP, "D2F", TGSI_OPCODE_D2F }, 239 { 1, 1, 0, 0, 0, 0, 0, COMP, "DABS", TGSI_OPCODE_DABS }, 240 { 1, 1, 0, 0, 0, 0, 0, COMP, "DNEG", TGSI_OPCODE_DNEG }, 241 { 1, 2, 0, 0, 0, 0, 0, COMP, "DADD", TGSI_OPCODE_DADD }, 242 { 1, 2, 0, 0, 0, 0, 0, COMP, "DMUL", TGSI_OPCODE_DMUL }, 243 { 1, 2, 0, 0, 0, 0, 0, COMP, "DMAX", TGSI_OPCODE_DMAX }, 244 { 1, 2, 0, 0, 0, 0, 0, COMP, "DMIN", TGSI_OPCODE_DMIN }, 245 { 1, 2, 0, 0, 0, 0, 0, COMP, "DSLT", TGSI_OPCODE_DSLT }, 246 { 1, 2, 0, 0, 0, 0, 0, COMP, "DSGE", TGSI_OPCODE_DSGE }, 247 { 1, 2, 0, 0, 0, 0, 0, COMP, "DSEQ", TGSI_OPCODE_DSEQ }, 248 { 1, 2, 0, 0, 0, 0, 0, COMP, "DSNE", TGSI_OPCODE_DSNE }, 249 { 1, 1, 0, 0, 0, 0, 0, COMP, "DRCP", TGSI_OPCODE_DRCP }, 250 { 1, 1, 0, 0, 0, 0, 0, COMP, "DSQRT", TGSI_OPCODE_DSQRT }, 251 { 1, 3, 0, 0, 0, 0, 0, COMP, "DMAD", TGSI_OPCODE_DMAD }, 252 { 1, 1, 0, 0, 0, 0, 0, COMP, "DFRAC", TGSI_OPCODE_DFRAC}, 253 { 1, 2, 0, 0, 0, 0, 0, COMP, "DLDEXP", TGSI_OPCODE_DLDEXP}, 254 { 2, 1, 0, 0, 0, 0, 0, COMP, "DFRACEXP", TGSI_OPCODE_DFRACEXP}, 255 { 1, 1, 0, 0, 0, 0, 0, COMP, "D2I", TGSI_OPCODE_D2I }, 256 { 1, 1, 0, 0, 0, 0, 0, COMP, "I2D", TGSI_OPCODE_I2D }, 257 { 1, 1, 0, 0, 0, 0, 0, COMP, "D2U", TGSI_OPCODE_D2U }, 258 { 1, 1, 0, 0, 0, 0, 0, COMP, "U2D", TGSI_OPCODE_U2D }, 259 { 1, 1, 0, 0, 0, 0, 0, COMP, "DRSQ", TGSI_OPCODE_DRSQ }, 260 { 1, 1, 0, 0, 0, 0, 0, COMP, "DTRUNC", TGSI_OPCODE_DTRUNC }, 261 { 1, 1, 0, 0, 0, 0, 0, COMP, "DCEIL", TGSI_OPCODE_DCEIL }, 262 { 1, 1, 0, 0, 0, 0, 0, COMP, "DFLR", TGSI_OPCODE_DFLR }, 263 { 1, 1, 0, 0, 0, 0, 0, COMP, "DROUND", TGSI_OPCODE_DROUND }, 264 { 1, 1, 0, 0, 0, 0, 0, COMP, "DSSG", TGSI_OPCODE_DSSG }, 265 { 1, 1, 0, 0, 0, 0, 0, COMP, "VOTE_ANY", TGSI_OPCODE_VOTE_ANY }, 266 { 1, 1, 0, 0, 0, 0, 0, COMP, "VOTE_ALL", TGSI_OPCODE_VOTE_ALL }, 267 { 1, 1, 0, 0, 0, 0, 0, COMP, "VOTE_EQ", TGSI_OPCODE_VOTE_EQ }, 268 { 1, 2, 0, 0, 0, 0, 0, COMP, "U64SEQ", TGSI_OPCODE_U64SEQ }, 269 { 1, 2, 0, 0, 0, 0, 0, COMP, "U64SNE", TGSI_OPCODE_U64SNE }, 270 { 1, 2, 0, 0, 0, 0, 0, COMP, "I64SLT", TGSI_OPCODE_I64SLT }, 271 { 1, 2, 0, 0, 0, 0, 0, COMP, "U64SLT", TGSI_OPCODE_U64SLT }, 272 { 1, 2, 0, 0, 0, 0, 0, COMP, "I64SGE", TGSI_OPCODE_I64SGE }, 273 { 1, 2, 0, 0, 0, 0, 0, COMP, "U64SGE", TGSI_OPCODE_U64SGE }, 274 { 1, 2, 0, 0, 0, 0, 0, COMP, "I64MIN", TGSI_OPCODE_I64MIN }, 275 { 1, 2, 0, 0, 0, 0, 0, COMP, "U64MIN", TGSI_OPCODE_U64MIN }, 276 { 1, 2, 0, 0, 0, 0, 0, COMP, "I64MAX", TGSI_OPCODE_I64MAX }, 277 { 1, 2, 0, 0, 0, 0, 0, COMP, "U64MAX", TGSI_OPCODE_U64MAX }, 278 { 1, 1, 0, 0, 0, 0, 0, COMP, "I64ABS", TGSI_OPCODE_I64ABS }, 279 { 1, 1, 0, 0, 0, 0, 0, COMP, "I64SSG", TGSI_OPCODE_I64SSG }, 280 { 1, 1, 0, 0, 0, 0, 0, COMP, "I64NEG", TGSI_OPCODE_I64NEG }, 281 { 1, 2, 0, 0, 0, 0, 0, COMP, "U64ADD", TGSI_OPCODE_U64ADD }, 282 { 1, 2, 0, 0, 0, 0, 0, COMP, "U64MUL", TGSI_OPCODE_U64MUL }, 283 { 1, 2, 0, 0, 0, 0, 0, COMP, "U64SHL", TGSI_OPCODE_U64SHL }, 284 { 1, 2, 0, 0, 0, 0, 0, COMP, "I64SHR", TGSI_OPCODE_I64SHR }, 285 { 1, 2, 0, 0, 0, 0, 0, COMP, "U64SHR", TGSI_OPCODE_U64SHR }, 286 { 1, 2, 0, 0, 0, 0, 0, COMP, "I64DIV", TGSI_OPCODE_I64DIV }, 287 { 1, 2, 0, 0, 0, 0, 0, COMP, "U64DIV", TGSI_OPCODE_U64DIV }, 288 { 1, 2, 0, 0, 0, 0, 0, COMP, "I64MOD", TGSI_OPCODE_I64MOD }, 289 { 1, 2, 0, 0, 0, 0, 0, COMP, "U64MOD", TGSI_OPCODE_U64MOD }, 290 { 1, 2, 0, 0, 0, 0, 0, COMP, "DDIV", TGSI_OPCODE_DDIV }, 291 }; 292 293 const struct tgsi_opcode_info * 294 tgsi_get_opcode_info( uint opcode ) 295 { 296 static boolean firsttime = 1; 297 298 if (firsttime) { 299 unsigned i; 300 firsttime = 0; 301 for (i = 0; i < ARRAY_SIZE(opcode_info); i++) 302 assert(opcode_info[i].opcode == i); 303 } 304 305 if (opcode < TGSI_OPCODE_LAST) 306 return &opcode_info[opcode]; 307 308 assert( 0 ); 309 return NULL; 310 } 311 312 313 const char * 314 tgsi_get_opcode_name( uint opcode ) 315 { 316 const struct tgsi_opcode_info *info = tgsi_get_opcode_info(opcode); 317 return info->mnemonic; 318 } 319 320 321 const char * 322 tgsi_get_processor_name( uint processor ) 323 { 324 switch (processor) { 325 case PIPE_SHADER_VERTEX: 326 return "vertex shader"; 327 case PIPE_SHADER_FRAGMENT: 328 return "fragment shader"; 329 case PIPE_SHADER_GEOMETRY: 330 return "geometry shader"; 331 case PIPE_SHADER_TESS_CTRL: 332 return "tessellation control shader"; 333 case PIPE_SHADER_TESS_EVAL: 334 return "tessellation evaluation shader"; 335 default: 336 return "unknown shader type!"; 337 } 338 } 339 340 /** 341 * Infer the type (of the dst) of the opcode. 342 * 343 * MOV and UCMP is special so return VOID 344 */ 345 static inline enum tgsi_opcode_type 346 tgsi_opcode_infer_type( uint opcode ) 347 { 348 switch (opcode) { 349 case TGSI_OPCODE_MOV: 350 case TGSI_OPCODE_UCMP: 351 return TGSI_TYPE_UNTYPED; 352 case TGSI_OPCODE_NOT: 353 case TGSI_OPCODE_SHL: 354 case TGSI_OPCODE_AND: 355 case TGSI_OPCODE_OR: 356 case TGSI_OPCODE_XOR: 357 case TGSI_OPCODE_SAD: /* XXX some src args may be signed for SAD ? */ 358 case TGSI_OPCODE_TXQ: 359 case TGSI_OPCODE_TXQ_LZ: 360 case TGSI_OPCODE_TXQS: 361 case TGSI_OPCODE_F2U: 362 case TGSI_OPCODE_UDIV: 363 case TGSI_OPCODE_UMAD: 364 case TGSI_OPCODE_UMAX: 365 case TGSI_OPCODE_UMIN: 366 case TGSI_OPCODE_UMOD: 367 case TGSI_OPCODE_UMUL: 368 case TGSI_OPCODE_USEQ: 369 case TGSI_OPCODE_USGE: 370 case TGSI_OPCODE_USHR: 371 case TGSI_OPCODE_USLT: 372 case TGSI_OPCODE_USNE: 373 case TGSI_OPCODE_SVIEWINFO: 374 case TGSI_OPCODE_UMUL_HI: 375 case TGSI_OPCODE_UBFE: 376 case TGSI_OPCODE_BFI: 377 case TGSI_OPCODE_BREV: 378 case TGSI_OPCODE_POPC: 379 case TGSI_OPCODE_LSB: 380 case TGSI_OPCODE_UMSB: 381 return TGSI_TYPE_UNSIGNED; 382 case TGSI_OPCODE_ARL: 383 case TGSI_OPCODE_ARR: 384 case TGSI_OPCODE_MOD: 385 case TGSI_OPCODE_F2I: 386 case TGSI_OPCODE_FSEQ: 387 case TGSI_OPCODE_FSGE: 388 case TGSI_OPCODE_FSLT: 389 case TGSI_OPCODE_FSNE: 390 case TGSI_OPCODE_IDIV: 391 case TGSI_OPCODE_IMAX: 392 case TGSI_OPCODE_IMIN: 393 case TGSI_OPCODE_INEG: 394 case TGSI_OPCODE_ISGE: 395 case TGSI_OPCODE_ISHR: 396 case TGSI_OPCODE_ISLT: 397 case TGSI_OPCODE_UADD: 398 case TGSI_OPCODE_UARL: 399 case TGSI_OPCODE_IABS: 400 case TGSI_OPCODE_ISSG: 401 case TGSI_OPCODE_IMUL_HI: 402 case TGSI_OPCODE_IBFE: 403 case TGSI_OPCODE_IMSB: 404 case TGSI_OPCODE_DSEQ: 405 case TGSI_OPCODE_DSGE: 406 case TGSI_OPCODE_DSLT: 407 case TGSI_OPCODE_DSNE: 408 case TGSI_OPCODE_U64SEQ: 409 case TGSI_OPCODE_U64SNE: 410 case TGSI_OPCODE_U64SLT: 411 case TGSI_OPCODE_U64SGE: 412 case TGSI_OPCODE_I64SLT: 413 case TGSI_OPCODE_I64SGE: 414 return TGSI_TYPE_SIGNED; 415 case TGSI_OPCODE_DADD: 416 case TGSI_OPCODE_DABS: 417 case TGSI_OPCODE_DFMA: 418 case TGSI_OPCODE_DNEG: 419 case TGSI_OPCODE_DMUL: 420 case TGSI_OPCODE_DMAX: 421 case TGSI_OPCODE_DDIV: 422 case TGSI_OPCODE_DMIN: 423 case TGSI_OPCODE_DRCP: 424 case TGSI_OPCODE_DSQRT: 425 case TGSI_OPCODE_DMAD: 426 case TGSI_OPCODE_DLDEXP: 427 case TGSI_OPCODE_DFRACEXP: 428 case TGSI_OPCODE_DFRAC: 429 case TGSI_OPCODE_DRSQ: 430 case TGSI_OPCODE_DTRUNC: 431 case TGSI_OPCODE_DCEIL: 432 case TGSI_OPCODE_DFLR: 433 case TGSI_OPCODE_DROUND: 434 case TGSI_OPCODE_DSSG: 435 case TGSI_OPCODE_F2D: 436 case TGSI_OPCODE_I2D: 437 case TGSI_OPCODE_U2D: 438 case TGSI_OPCODE_U642D: 439 case TGSI_OPCODE_I642D: 440 return TGSI_TYPE_DOUBLE; 441 case TGSI_OPCODE_U64MAX: 442 case TGSI_OPCODE_U64MIN: 443 case TGSI_OPCODE_U64ADD: 444 case TGSI_OPCODE_U64MUL: 445 case TGSI_OPCODE_U64DIV: 446 case TGSI_OPCODE_U64MOD: 447 case TGSI_OPCODE_U64SHL: 448 case TGSI_OPCODE_U64SHR: 449 case TGSI_OPCODE_F2U64: 450 case TGSI_OPCODE_D2U64: 451 return TGSI_TYPE_UNSIGNED64; 452 case TGSI_OPCODE_I64MAX: 453 case TGSI_OPCODE_I64MIN: 454 case TGSI_OPCODE_I64ABS: 455 case TGSI_OPCODE_I64SSG: 456 case TGSI_OPCODE_I64NEG: 457 case TGSI_OPCODE_I64SHR: 458 case TGSI_OPCODE_I64DIV: 459 case TGSI_OPCODE_I64MOD: 460 case TGSI_OPCODE_F2I64: 461 case TGSI_OPCODE_U2I64: 462 case TGSI_OPCODE_I2I64: 463 case TGSI_OPCODE_D2I64: 464 return TGSI_TYPE_SIGNED64; 465 default: 466 return TGSI_TYPE_FLOAT; 467 } 468 } 469 470 /* 471 * infer the source type of a TGSI opcode. 472 */ 473 enum tgsi_opcode_type 474 tgsi_opcode_infer_src_type( uint opcode ) 475 { 476 switch (opcode) { 477 case TGSI_OPCODE_UIF: 478 case TGSI_OPCODE_TXF: 479 case TGSI_OPCODE_BREAKC: 480 case TGSI_OPCODE_U2F: 481 case TGSI_OPCODE_U2D: 482 case TGSI_OPCODE_UADD: 483 case TGSI_OPCODE_SWITCH: 484 case TGSI_OPCODE_CASE: 485 case TGSI_OPCODE_SAMPLE_I: 486 case TGSI_OPCODE_SAMPLE_I_MS: 487 case TGSI_OPCODE_UMUL_HI: 488 case TGSI_OPCODE_UP2H: 489 case TGSI_OPCODE_U2I64: 490 case TGSI_OPCODE_MEMBAR: 491 return TGSI_TYPE_UNSIGNED; 492 case TGSI_OPCODE_IMUL_HI: 493 case TGSI_OPCODE_I2F: 494 case TGSI_OPCODE_I2D: 495 case TGSI_OPCODE_I2I64: 496 return TGSI_TYPE_SIGNED; 497 case TGSI_OPCODE_ARL: 498 case TGSI_OPCODE_ARR: 499 case TGSI_OPCODE_TXQ_LZ: 500 case TGSI_OPCODE_F2D: 501 case TGSI_OPCODE_F2I: 502 case TGSI_OPCODE_F2U: 503 case TGSI_OPCODE_FSEQ: 504 case TGSI_OPCODE_FSGE: 505 case TGSI_OPCODE_FSLT: 506 case TGSI_OPCODE_FSNE: 507 case TGSI_OPCODE_UCMP: 508 case TGSI_OPCODE_F2U64: 509 case TGSI_OPCODE_F2I64: 510 return TGSI_TYPE_FLOAT; 511 case TGSI_OPCODE_D2F: 512 case TGSI_OPCODE_D2U: 513 case TGSI_OPCODE_D2I: 514 case TGSI_OPCODE_DSEQ: 515 case TGSI_OPCODE_DSGE: 516 case TGSI_OPCODE_DSLT: 517 case TGSI_OPCODE_DSNE: 518 case TGSI_OPCODE_D2U64: 519 case TGSI_OPCODE_D2I64: 520 return TGSI_TYPE_DOUBLE; 521 case TGSI_OPCODE_U64SEQ: 522 case TGSI_OPCODE_U64SNE: 523 case TGSI_OPCODE_U64SLT: 524 case TGSI_OPCODE_U64SGE: 525 case TGSI_OPCODE_U642F: 526 case TGSI_OPCODE_U642D: 527 return TGSI_TYPE_UNSIGNED64; 528 case TGSI_OPCODE_I64SLT: 529 case TGSI_OPCODE_I64SGE: 530 case TGSI_OPCODE_I642F: 531 case TGSI_OPCODE_I642D: 532 return TGSI_TYPE_SIGNED64; 533 default: 534 return tgsi_opcode_infer_type(opcode); 535 } 536 } 537 538 /* 539 * infer the destination type of a TGSI opcode. 540 */ 541 enum tgsi_opcode_type 542 tgsi_opcode_infer_dst_type( uint opcode ) 543 { 544 return tgsi_opcode_infer_type(opcode); 545 } 546
