1 /* 2 * Mesa 3-D graphics library 3 * 4 * Copyright (C) 2012-2013 LunarG, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Chia-I Wu <olv (at) lunarg.com> 26 */ 27 28 #include "genhw/genhw.h" 29 #include "intel_winsys.h" 30 31 #include "ilo_debug.h" 32 #include "ilo_dev.h" 33 34 /** 35 * Initialize the \p dev from \p winsys. 36 */ 37 bool 38 ilo_dev_init(struct ilo_dev *dev, struct intel_winsys *winsys) 39 { 40 const struct intel_winsys_info *info; 41 42 assert(ilo_is_zeroed(dev, sizeof(*dev))); 43 44 info = intel_winsys_get_info(winsys); 45 46 dev->winsys = winsys; 47 dev->devid = info->devid; 48 dev->aperture_total = info->aperture_total; 49 dev->aperture_mappable = info->aperture_mappable; 50 dev->has_llc = info->has_llc; 51 dev->has_address_swizzling = info->has_address_swizzling; 52 dev->has_logical_context = info->has_logical_context; 53 dev->has_ppgtt = info->has_ppgtt; 54 dev->has_timestamp = info->has_timestamp; 55 dev->has_gen7_sol_reset = info->has_gen7_sol_reset; 56 57 if (!dev->has_logical_context) { 58 ilo_err("missing hardware logical context support\n"); 59 return false; 60 } 61 62 /* 63 * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT 64 * writes on GEN6. 65 * 66 * From the Sandy Bridge PRM, volume 1 part 3, page 101: 67 * 68 * "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all 69 * code is in a secure environment, independent of address space. 70 * Under this condition, this bit only specifies the address space 71 * (GGTT or PPGTT). All commands are executed "as-is"" 72 * 73 * We need PPGTT to be enabled on GEN6 too. 74 */ 75 if (!dev->has_ppgtt) { 76 /* experiments show that it does not really matter... */ 77 ilo_warn("PPGTT disabled\n"); 78 } 79 80 if (gen_is_bdw(info->devid) || gen_is_chv(info->devid)) { 81 dev->gen_opaque = ILO_GEN(8); 82 dev->gt = (gen_is_bdw(info->devid)) ? gen_get_bdw_gt(info->devid) : 1; 83 /* XXX random values */ 84 if (dev->gt == 3) { 85 dev->eu_count = 48; 86 dev->thread_count = 336; 87 dev->urb_size = 384 * 1024; 88 } else if (dev->gt == 2) { 89 dev->eu_count = 24; 90 dev->thread_count = 168; 91 dev->urb_size = 384 * 1024; 92 } else { 93 dev->eu_count = 12; 94 dev->thread_count = 84; 95 dev->urb_size = 192 * 1024; 96 } 97 } else if (gen_is_hsw(info->devid)) { 98 /* 99 * From the Haswell PRM, volume 4, page 8: 100 * 101 * "Description GT3 GT2 GT1.5 GT1 102 * (...) 103 * EUs (Total) 40 20 12 10 104 * Threads (Total) 280 140 84 70 105 * (...) 106 * URB Size (max, within L3$) 512KB 256KB 256KB 128KB 107 */ 108 dev->gen_opaque = ILO_GEN(7.5); 109 dev->gt = gen_get_hsw_gt(info->devid); 110 if (dev->gt == 3) { 111 dev->eu_count = 40; 112 dev->thread_count = 280; 113 dev->urb_size = 512 * 1024; 114 } else if (dev->gt == 2) { 115 dev->eu_count = 20; 116 dev->thread_count = 140; 117 dev->urb_size = 256 * 1024; 118 } else { 119 dev->eu_count = 10; 120 dev->thread_count = 70; 121 dev->urb_size = 128 * 1024; 122 } 123 } else if (gen_is_ivb(info->devid) || gen_is_vlv(info->devid)) { 124 /* 125 * From the Ivy Bridge PRM, volume 1 part 1, page 18: 126 * 127 * "Device # of EUs #Threads/EU 128 * Ivy Bridge (GT2) 16 8 129 * Ivy Bridge (GT1) 6 6" 130 * 131 * From the Ivy Bridge PRM, volume 4 part 2, page 17: 132 * 133 * "URB Size URB Rows URB Rows when SLM Enabled 134 * 128k 4096 2048 135 * 256k 8096 4096" 136 */ 137 dev->gen_opaque = ILO_GEN(7); 138 dev->gt = (gen_is_ivb(info->devid)) ? gen_get_ivb_gt(info->devid) : 1; 139 if (dev->gt == 2) { 140 dev->eu_count = 16; 141 dev->thread_count = 128; 142 dev->urb_size = 256 * 1024; 143 } else { 144 dev->eu_count = 6; 145 dev->thread_count = 36; 146 dev->urb_size = 128 * 1024; 147 } 148 } else if (gen_is_snb(info->devid)) { 149 /* 150 * From the Sandy Bridge PRM, volume 1 part 1, page 22: 151 * 152 * "Device # of EUs #Threads/EU 153 * SNB GT2 12 5 154 * SNB GT1 6 4" 155 * 156 * From the Sandy Bridge PRM, volume 4 part 2, page 18: 157 * 158 * "[DevSNB]: The GT1 product's URB provides 32KB of storage, 159 * arranged as 1024 256-bit rows. The GT2 product's URB provides 160 * 64KB of storage, arranged as 2048 256-bit rows. A row 161 * corresponds in size to an EU GRF register. Read/write access to 162 * the URB is generally supported on a row-granular basis." 163 */ 164 dev->gen_opaque = ILO_GEN(6); 165 dev->gt = gen_get_snb_gt(info->devid); 166 if (dev->gt == 2) { 167 dev->eu_count = 12; 168 dev->thread_count = 60; 169 dev->urb_size = 64 * 1024; 170 } else { 171 dev->eu_count = 6; 172 dev->thread_count = 24; 173 dev->urb_size = 32 * 1024; 174 } 175 } else { 176 ilo_err("unknown GPU generation\n"); 177 return false; 178 } 179 180 return true; 181 } 182
