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      1 /*
      2  * Copyright  2015 Intel Corporation
      3  *
      4  * Permission is hereby granted, free of charge, to any person obtaining a
      5  * copy of this software and associated documentation files (the "Software"),
      6  * to deal in the Software without restriction, including without limitation
      7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8  * and/or sell copies of the Software, and to permit persons to whom the
      9  * Software is furnished to do so, subject to the following conditions:
     10  *
     11  * The above copyright notice and this permission notice (including the next
     12  * paragraph) shall be included in all copies or substantial portions of the
     13  * Software.
     14  *
     15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
     21  * IN THE SOFTWARE.
     22  */
     23 
     24 #include <assert.h>
     25 #include <stdbool.h>
     26 #include <string.h>
     27 #include <unistd.h>
     28 #include <fcntl.h>
     29 
     30 #include "anv_private.h"
     31 #include "vk_format_info.h"
     32 
     33 #include "genxml/gen_macros.h"
     34 #include "genxml/genX_pack.h"
     35 
     36 static inline int64_t
     37 clamp_int64(int64_t x, int64_t min, int64_t max)
     38 {
     39    if (x < min)
     40       return min;
     41    else if (x < max)
     42       return x;
     43    else
     44       return max;
     45 }
     46 
     47 #if GEN_GEN == 7 && !GEN_IS_HASWELL
     48 void
     49 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
     50 {
     51    uint32_t count = cmd_buffer->state.dynamic.scissor.count;
     52    const VkRect2D *scissors =  cmd_buffer->state.dynamic.scissor.scissors;
     53    struct anv_state scissor_state =
     54       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
     55 
     56    for (uint32_t i = 0; i < count; i++) {
     57       const VkRect2D *s = &scissors[i];
     58 
     59       /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
     60        * ymax < ymin for empty clips.  In case clip x, y, width height are all
     61        * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
     62        * what we want. Just special case empty clips and produce a canonical
     63        * empty clip. */
     64       static const struct GEN7_SCISSOR_RECT empty_scissor = {
     65          .ScissorRectangleYMin = 1,
     66          .ScissorRectangleXMin = 1,
     67          .ScissorRectangleYMax = 0,
     68          .ScissorRectangleXMax = 0
     69       };
     70 
     71       const int max = 0xffff;
     72       struct GEN7_SCISSOR_RECT scissor = {
     73          /* Do this math using int64_t so overflow gets clamped correctly. */
     74          .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
     75          .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
     76          .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
     77          .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
     78       };
     79 
     80       if (s->extent.width <= 0 || s->extent.height <= 0) {
     81          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
     82                                 &empty_scissor);
     83       } else {
     84          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
     85       }
     86    }
     87 
     88    anv_batch_emit(&cmd_buffer->batch,
     89                   GEN7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) {
     90       ssp.ScissorRectPointer = scissor_state.offset;
     91    }
     92 
     93    if (!cmd_buffer->device->info.has_llc)
     94       anv_state_clflush(scissor_state);
     95 }
     96 #endif
     97 
     98 static const uint32_t vk_to_gen_index_type[] = {
     99    [VK_INDEX_TYPE_UINT16]                       = INDEX_WORD,
    100    [VK_INDEX_TYPE_UINT32]                       = INDEX_DWORD,
    101 };
    102 
    103 static const uint32_t restart_index_for_type[] = {
    104    [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
    105    [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
    106 };
    107 
    108 void genX(CmdBindIndexBuffer)(
    109     VkCommandBuffer                             commandBuffer,
    110     VkBuffer                                    _buffer,
    111     VkDeviceSize                                offset,
    112     VkIndexType                                 indexType)
    113 {
    114    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
    115    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
    116 
    117    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
    118    if (GEN_IS_HASWELL)
    119       cmd_buffer->state.restart_index = restart_index_for_type[indexType];
    120    cmd_buffer->state.gen7.index_buffer = buffer;
    121    cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
    122    cmd_buffer->state.gen7.index_offset = offset;
    123 }
    124 
    125 static uint32_t
    126 get_depth_format(struct anv_cmd_buffer *cmd_buffer)
    127 {
    128    const struct anv_render_pass *pass = cmd_buffer->state.pass;
    129    const struct anv_subpass *subpass = cmd_buffer->state.subpass;
    130 
    131    if (subpass->depth_stencil_attachment >= pass->attachment_count)
    132       return D16_UNORM;
    133 
    134    struct anv_render_pass_attachment *att =
    135       &pass->attachments[subpass->depth_stencil_attachment];
    136 
    137    switch (att->format) {
    138    case VK_FORMAT_D16_UNORM:
    139    case VK_FORMAT_D16_UNORM_S8_UINT:
    140       return D16_UNORM;
    141 
    142    case VK_FORMAT_X8_D24_UNORM_PACK32:
    143    case VK_FORMAT_D24_UNORM_S8_UINT:
    144       return D24_UNORM_X8_UINT;
    145 
    146    case VK_FORMAT_D32_SFLOAT:
    147    case VK_FORMAT_D32_SFLOAT_S8_UINT:
    148       return D32_FLOAT;
    149 
    150    default:
    151       return D16_UNORM;
    152    }
    153 }
    154 
    155 void
    156 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
    157 {
    158    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
    159 
    160    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
    161                                   ANV_CMD_DIRTY_RENDER_TARGETS |
    162                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
    163                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
    164       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
    165       struct GENX(3DSTATE_SF) sf = {
    166          GENX(3DSTATE_SF_header),
    167          .DepthBufferSurfaceFormat = get_depth_format(cmd_buffer),
    168          .LineWidth = cmd_buffer->state.dynamic.line_width,
    169          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
    170          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
    171          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
    172       };
    173       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
    174 
    175       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
    176    }
    177 
    178    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
    179                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
    180       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
    181       struct anv_state cc_state =
    182          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
    183                                             GENX(COLOR_CALC_STATE_length) * 4,
    184                                             64);
    185       struct GENX(COLOR_CALC_STATE) cc = {
    186          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
    187          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
    188          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
    189          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
    190          .StencilReferenceValue = d->stencil_reference.front & 0xff,
    191          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
    192       };
    193       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
    194       if (!cmd_buffer->device->info.has_llc)
    195          anv_state_clflush(cc_state);
    196 
    197       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
    198          ccp.ColorCalcStatePointer = cc_state.offset;
    199       }
    200    }
    201 
    202    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
    203                                   ANV_CMD_DIRTY_RENDER_TARGETS |
    204                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
    205                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
    206       uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
    207       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
    208 
    209       struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
    210          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
    211          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
    212 
    213          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
    214          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
    215       };
    216       GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
    217 
    218       struct anv_state ds_state =
    219          anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
    220                                       pipeline->gen7.depth_stencil_state,
    221                                       GENX(DEPTH_STENCIL_STATE_length), 64);
    222 
    223       anv_batch_emit(&cmd_buffer->batch,
    224                      GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), dsp) {
    225          dsp.PointertoDEPTH_STENCIL_STATE = ds_state.offset;
    226       }
    227    }
    228 
    229    if (cmd_buffer->state.gen7.index_buffer &&
    230        cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
    231                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
    232       struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
    233       uint32_t offset = cmd_buffer->state.gen7.index_offset;
    234 
    235 #if GEN_IS_HASWELL
    236       anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) {
    237          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
    238          vf.CutIndex                   = cmd_buffer->state.restart_index;
    239       }
    240 #endif
    241 
    242       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
    243 #if !GEN_IS_HASWELL
    244          ib.CutIndexEnable             = pipeline->primitive_restart;
    245 #endif
    246          ib.IndexFormat                = cmd_buffer->state.gen7.index_type;
    247          ib.MemoryObjectControlState   = GENX(MOCS);
    248 
    249          ib.BufferStartingAddress =
    250             (struct anv_address) { buffer->bo, buffer->offset + offset };
    251          ib.BufferEndingAddress =
    252             (struct anv_address) { buffer->bo, buffer->offset + buffer->size };
    253       }
    254    }
    255 
    256    cmd_buffer->state.dirty = 0;
    257 }
    258 
    259 void genX(CmdSetEvent)(
    260     VkCommandBuffer                             commandBuffer,
    261     VkEvent                                     event,
    262     VkPipelineStageFlags                        stageMask)
    263 {
    264    stub();
    265 }
    266 
    267 void genX(CmdResetEvent)(
    268     VkCommandBuffer                             commandBuffer,
    269     VkEvent                                     event,
    270     VkPipelineStageFlags                        stageMask)
    271 {
    272    stub();
    273 }
    274 
    275 void genX(CmdWaitEvents)(
    276     VkCommandBuffer                             commandBuffer,
    277     uint32_t                                    eventCount,
    278     const VkEvent*                              pEvents,
    279     VkPipelineStageFlags                        srcStageMask,
    280     VkPipelineStageFlags                        destStageMask,
    281     uint32_t                                    memoryBarrierCount,
    282     const VkMemoryBarrier*                      pMemoryBarriers,
    283     uint32_t                                    bufferMemoryBarrierCount,
    284     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
    285     uint32_t                                    imageMemoryBarrierCount,
    286     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
    287 {
    288    stub();
    289 
    290    genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
    291                             false, /* byRegion */
    292                             memoryBarrierCount, pMemoryBarriers,
    293                             bufferMemoryBarrierCount, pBufferMemoryBarriers,
    294                             imageMemoryBarrierCount, pImageMemoryBarriers);
    295 }
    296