1 /* 2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3 4 The Weather Channel (TM) funded Tungsten Graphics to develop the 5 initial release of the Radeon 8500 driver under the XFree86 license. 6 This notice must be preserved. 7 8 Permission is hereby granted, free of charge, to any person obtaining 9 a copy of this software and associated documentation files (the 10 "Software"), to deal in the Software without restriction, including 11 without limitation the rights to use, copy, modify, merge, publish, 12 distribute, sublicense, and/or sell copies of the Software, and to 13 permit persons to whom the Software is furnished to do so, subject to 14 the following conditions: 15 16 The above copyright notice and this permission notice (including the 17 next paragraph) shall be included in all copies or substantial 18 portions of the Software. 19 20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28 **************************************************************************/ 29 30 /* 31 * Authors: 32 * Keith Whitwell <keithw (at) vmware.com> 33 */ 34 35 #ifndef __R200_IOCTL_H__ 36 #define __R200_IOCTL_H__ 37 38 #include "radeon_bo_gem.h" 39 #include "radeon_cs_gem.h" 40 41 #include "xf86drm.h" 42 #include "drm.h" 43 #include "radeon_drm.h" 44 45 extern void r200EmitMaxVtxIndex(r200ContextPtr rmesa, int count); 46 extern void r200EmitVertexAOS( r200ContextPtr rmesa, 47 GLuint vertex_size, 48 struct radeon_bo *bo, 49 GLuint offset ); 50 51 extern void r200EmitVbufPrim( r200ContextPtr rmesa, 52 GLuint primitive, 53 GLuint vertex_nr ); 54 55 extern void r200FlushElts(struct gl_context *ctx); 56 57 extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, 58 GLuint primitive, 59 GLuint min_nr ); 60 61 extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset); 62 63 extern void r200InitIoctlFuncs( struct dd_function_table *functions ); 64 65 void r200SetUpAtomList( r200ContextPtr rmesa ); 66 67 /* ================================================================ 68 * Helper macros: 69 */ 70 71 /* Close off the last primitive, if it exists. 72 */ 73 #define R200_NEWPRIM( rmesa ) \ 74 do { \ 75 if ( rmesa->radeon.dma.flush ) \ 76 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); \ 77 } while (0) 78 79 /* Can accommodate several state changes and primitive changes without 80 * actually firing the buffer. 81 */ 82 #define R200_STATECHANGE( rmesa, ATOM ) \ 83 do { \ 84 R200_NEWPRIM( rmesa ); \ 85 rmesa->hw.ATOM.dirty = GL_TRUE; \ 86 rmesa->radeon.hw.is_dirty = GL_TRUE; \ 87 } while (0) 88 89 #define R200_SET_STATE( rmesa, ATOM, index, newvalue ) \ 90 do { \ 91 uint32_t __index = (index); \ 92 uint32_t __dword = (newvalue); \ 93 if (__dword != (rmesa)->hw.ATOM.cmd[__index]) { \ 94 R200_STATECHANGE( (rmesa), ATOM ); \ 95 (rmesa)->hw.ATOM.cmd[__index] = __dword; \ 96 } \ 97 } while(0) 98 99 #define R200_DB_STATE( ATOM ) \ 100 memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd, \ 101 rmesa->hw.ATOM.cmd_size * 4) 102 103 static inline int R200_DB_STATECHANGE( 104 r200ContextPtr rmesa, 105 struct radeon_state_atom *atom ) 106 { 107 if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) { 108 GLuint *tmp; 109 R200_NEWPRIM( rmesa ); 110 atom->dirty = GL_TRUE; 111 rmesa->radeon.hw.is_dirty = GL_TRUE; 112 tmp = atom->cmd; 113 atom->cmd = atom->lastcmd; 114 atom->lastcmd = tmp; 115 return 1; 116 } 117 else 118 return 0; 119 } 120 121 122 /* Command lengths. Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ 123 * are available, you will also be adding an rmesa->state.max_state_size because 124 * r200EmitState is called from within r200EmitVbufPrim and r200FlushElts. 125 */ 126 #define AOS_BUFSZ(nr) ((3 + ((nr / 2) * 3) + ((nr & 1) * 2) + nr*2)) 127 #define VERT_AOS_BUFSZ (5) 128 #define ELTS_BUFSZ(nr) (12 + nr * 2) 129 #define VBUF_BUFSZ (3) 130 #define SCISSOR_BUFSZ (8) 131 #define INDEX_BUFSZ (8+2) 132 133 static inline uint32_t cmdpacket3(int cmd_type) 134 { 135 drm_radeon_cmd_header_t cmd; 136 137 cmd.i = 0; 138 cmd.header.cmd_type = cmd_type; 139 140 return (uint32_t)cmd.i; 141 142 } 143 144 #define OUT_BATCH_PACKET3(packet, num_extra) do { \ 145 OUT_BATCH(CP_PACKET2); \ 146 OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ 147 } while(0) 148 149 #define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do { \ 150 OUT_BATCH(CP_PACKET2); \ 151 OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ 152 } while(0) 153 154 155 #endif /* __R200_IOCTL_H__ */ 156