1 /* 2 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 3 VA Linux Systems Inc., Fremont, California. 4 5 All Rights Reserved. 6 7 Permission is hereby granted, free of charge, to any person obtaining 8 a copy of this software and associated documentation files (the 9 "Software"), to deal in the Software without restriction, including 10 without limitation the rights to use, copy, modify, merge, publish, 11 distribute, sublicense, and/or sell copies of the Software, and to 12 permit persons to whom the Software is furnished to do so, subject to 13 the following conditions: 14 15 The above copyright notice and this permission notice (including the 16 next paragraph) shall be included in all copies or substantial 17 portions of the Software. 18 19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 22 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 23 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 24 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 25 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 */ 27 28 /* 29 * Authors: 30 * Gareth Hughes <gareth (at) valinux.com> 31 * Brian Paul <brianp (at) valinux.com> 32 */ 33 34 #include "main/glheader.h" 35 #include "main/imports.h" 36 #include "main/context.h" 37 #include "main/enums.h" 38 #include "main/image.h" 39 #include "main/teximage.h" 40 #include "main/texobj.h" 41 42 #include "radeon_context.h" 43 #include "radeon_mipmap_tree.h" 44 #include "radeon_ioctl.h" 45 #include "radeon_tex.h" 46 47 #include "xmlpool.h" 48 49 50 51 /** 52 * Set the texture wrap modes. 53 * 54 * \param t Texture object whose wrap modes are to be set 55 * \param swrap Wrap mode for the \a s texture coordinate 56 * \param twrap Wrap mode for the \a t texture coordinate 57 */ 58 59 static void radeonSetTexWrap( radeonTexObjPtr t, GLenum swrap, GLenum twrap ) 60 { 61 GLboolean is_clamp = GL_FALSE; 62 GLboolean is_clamp_to_border = GL_FALSE; 63 64 t->pp_txfilter &= ~(RADEON_CLAMP_S_MASK | RADEON_CLAMP_T_MASK | RADEON_BORDER_MODE_D3D); 65 66 switch ( swrap ) { 67 case GL_REPEAT: 68 t->pp_txfilter |= RADEON_CLAMP_S_WRAP; 69 break; 70 case GL_CLAMP: 71 t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL; 72 is_clamp = GL_TRUE; 73 break; 74 case GL_CLAMP_TO_EDGE: 75 t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_LAST; 76 break; 77 case GL_CLAMP_TO_BORDER: 78 t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL; 79 is_clamp_to_border = GL_TRUE; 80 break; 81 case GL_MIRRORED_REPEAT: 82 t->pp_txfilter |= RADEON_CLAMP_S_MIRROR; 83 break; 84 case GL_MIRROR_CLAMP_EXT: 85 t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL; 86 is_clamp = GL_TRUE; 87 break; 88 case GL_MIRROR_CLAMP_TO_EDGE_EXT: 89 t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_LAST; 90 break; 91 case GL_MIRROR_CLAMP_TO_BORDER_EXT: 92 t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL; 93 is_clamp_to_border = GL_TRUE; 94 break; 95 default: 96 _mesa_problem(NULL, "bad S wrap mode in %s", __func__); 97 } 98 99 if (t->base.Target != GL_TEXTURE_1D) { 100 switch ( twrap ) { 101 case GL_REPEAT: 102 t->pp_txfilter |= RADEON_CLAMP_T_WRAP; 103 break; 104 case GL_CLAMP: 105 t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_GL; 106 is_clamp = GL_TRUE; 107 break; 108 case GL_CLAMP_TO_EDGE: 109 t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_LAST; 110 break; 111 case GL_CLAMP_TO_BORDER: 112 t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_GL; 113 is_clamp_to_border = GL_TRUE; 114 break; 115 case GL_MIRRORED_REPEAT: 116 t->pp_txfilter |= RADEON_CLAMP_T_MIRROR; 117 break; 118 case GL_MIRROR_CLAMP_EXT: 119 t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_GL; 120 is_clamp = GL_TRUE; 121 break; 122 case GL_MIRROR_CLAMP_TO_EDGE_EXT: 123 t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_LAST; 124 break; 125 case GL_MIRROR_CLAMP_TO_BORDER_EXT: 126 t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_GL; 127 is_clamp_to_border = GL_TRUE; 128 break; 129 default: 130 _mesa_problem(NULL, "bad T wrap mode in %s", __func__); 131 } 132 } 133 134 if ( is_clamp_to_border ) { 135 t->pp_txfilter |= RADEON_BORDER_MODE_D3D; 136 } 137 138 t->border_fallback = (is_clamp && is_clamp_to_border); 139 } 140 141 static void radeonSetTexMaxAnisotropy( radeonTexObjPtr t, GLfloat max ) 142 { 143 t->pp_txfilter &= ~RADEON_MAX_ANISO_MASK; 144 145 if ( max == 1.0 ) { 146 t->pp_txfilter |= RADEON_MAX_ANISO_1_TO_1; 147 } else if ( max <= 2.0 ) { 148 t->pp_txfilter |= RADEON_MAX_ANISO_2_TO_1; 149 } else if ( max <= 4.0 ) { 150 t->pp_txfilter |= RADEON_MAX_ANISO_4_TO_1; 151 } else if ( max <= 8.0 ) { 152 t->pp_txfilter |= RADEON_MAX_ANISO_8_TO_1; 153 } else { 154 t->pp_txfilter |= RADEON_MAX_ANISO_16_TO_1; 155 } 156 } 157 158 /** 159 * Set the texture magnification and minification modes. 160 * 161 * \param t Texture whose filter modes are to be set 162 * \param minf Texture minification mode 163 * \param magf Texture magnification mode 164 */ 165 166 static void radeonSetTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf ) 167 { 168 GLuint anisotropy = (t->pp_txfilter & RADEON_MAX_ANISO_MASK); 169 170 /* Force revalidation to account for switches from/to mipmapping. */ 171 t->validated = GL_FALSE; 172 173 t->pp_txfilter &= ~(RADEON_MIN_FILTER_MASK | RADEON_MAG_FILTER_MASK); 174 175 /* r100 chips can't handle mipmaps/aniso for cubemap/volume textures */ 176 if ( t->base.Target == GL_TEXTURE_CUBE_MAP ) { 177 switch ( minf ) { 178 case GL_NEAREST: 179 case GL_NEAREST_MIPMAP_NEAREST: 180 case GL_NEAREST_MIPMAP_LINEAR: 181 t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST; 182 break; 183 case GL_LINEAR: 184 case GL_LINEAR_MIPMAP_NEAREST: 185 case GL_LINEAR_MIPMAP_LINEAR: 186 t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR; 187 break; 188 default: 189 break; 190 } 191 } 192 else if ( anisotropy == RADEON_MAX_ANISO_1_TO_1 ) { 193 switch ( minf ) { 194 case GL_NEAREST: 195 t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST; 196 break; 197 case GL_LINEAR: 198 t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR; 199 break; 200 case GL_NEAREST_MIPMAP_NEAREST: 201 t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST_MIP_NEAREST; 202 break; 203 case GL_NEAREST_MIPMAP_LINEAR: 204 t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR_MIP_NEAREST; 205 break; 206 case GL_LINEAR_MIPMAP_NEAREST: 207 t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST_MIP_LINEAR; 208 break; 209 case GL_LINEAR_MIPMAP_LINEAR: 210 t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR_MIP_LINEAR; 211 break; 212 } 213 } else { 214 switch ( minf ) { 215 case GL_NEAREST: 216 t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST; 217 break; 218 case GL_LINEAR: 219 t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_LINEAR; 220 break; 221 case GL_NEAREST_MIPMAP_NEAREST: 222 case GL_LINEAR_MIPMAP_NEAREST: 223 t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST; 224 break; 225 case GL_NEAREST_MIPMAP_LINEAR: 226 case GL_LINEAR_MIPMAP_LINEAR: 227 t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR; 228 break; 229 } 230 } 231 232 switch ( magf ) { 233 case GL_NEAREST: 234 t->pp_txfilter |= RADEON_MAG_FILTER_NEAREST; 235 break; 236 case GL_LINEAR: 237 t->pp_txfilter |= RADEON_MAG_FILTER_LINEAR; 238 break; 239 } 240 } 241 242 static void radeonSetTexBorderColor( radeonTexObjPtr t, const GLfloat color[4] ) 243 { 244 GLubyte c[4]; 245 CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]); 246 CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]); 247 CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]); 248 CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]); 249 t->pp_border_color = radeonPackColor( 4, c[0], c[1], c[2], c[3] ); 250 } 251 252 #define SCALED_FLOAT_TO_BYTE( x, scale ) \ 253 (((GLuint)((255.0F / scale) * (x))) / 2) 254 255 static void radeonTexEnv( struct gl_context *ctx, GLenum target, 256 GLenum pname, const GLfloat *param ) 257 { 258 r100ContextPtr rmesa = R100_CONTEXT(ctx); 259 GLuint unit = ctx->Texture.CurrentUnit; 260 struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; 261 262 if ( RADEON_DEBUG & RADEON_STATE ) { 263 fprintf( stderr, "%s( %s )\n", 264 __func__, _mesa_enum_to_string( pname ) ); 265 } 266 267 switch ( pname ) { 268 case GL_TEXTURE_ENV_COLOR: { 269 GLubyte c[4]; 270 GLuint envColor; 271 _mesa_unclamped_float_rgba_to_ubyte(c, texUnit->EnvColor); 272 envColor = radeonPackColor( 4, c[0], c[1], c[2], c[3] ); 273 if ( rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] != envColor ) { 274 RADEON_STATECHANGE( rmesa, tex[unit] ); 275 rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] = envColor; 276 } 277 break; 278 } 279 280 case GL_TEXTURE_LOD_BIAS_EXT: { 281 GLfloat bias, min; 282 GLuint b; 283 284 /* The Radeon's LOD bias is a signed 2's complement value with a 285 * range of -1.0 <= bias < 4.0. We break this into two linear 286 * functions, one mapping [-1.0,0.0] to [-128,0] and one mapping 287 * [0.0,4.0] to [0,127]. 288 */ 289 min = driQueryOptionb (&rmesa->radeon.optionCache, "no_neg_lod_bias") ? 290 0.0 : -1.0; 291 bias = CLAMP( *param, min, 4.0 ); 292 if ( bias == 0 ) { 293 b = 0; 294 } else if ( bias > 0 ) { 295 b = ((GLuint)SCALED_FLOAT_TO_BYTE( bias, 4.0 )) << RADEON_LOD_BIAS_SHIFT; 296 } else { 297 b = ((GLuint)SCALED_FLOAT_TO_BYTE( bias, 1.0 )) << RADEON_LOD_BIAS_SHIFT; 298 } 299 if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] & RADEON_LOD_BIAS_MASK) != b ) { 300 RADEON_STATECHANGE( rmesa, tex[unit] ); 301 rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] &= ~RADEON_LOD_BIAS_MASK; 302 rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] |= (b & RADEON_LOD_BIAS_MASK); 303 } 304 break; 305 } 306 307 default: 308 return; 309 } 310 } 311 312 void radeonTexUpdateParameters(struct gl_context *ctx, GLuint unit) 313 { 314 struct gl_sampler_object *samp = _mesa_get_samplerobj(ctx, unit); 315 radeonTexObj* t = radeon_tex_obj(ctx->Texture.Unit[unit]._Current); 316 317 radeonSetTexMaxAnisotropy(t , samp->MaxAnisotropy); 318 radeonSetTexFilter(t, samp->MinFilter, samp->MagFilter); 319 radeonSetTexWrap(t, samp->WrapS, samp->WrapT); 320 radeonSetTexBorderColor(t, samp->BorderColor.f); 321 } 322 323 324 /** 325 * Changes variables and flags for a state update, which will happen at the 326 * next UpdateTextureState 327 */ 328 329 static void radeonTexParameter( struct gl_context *ctx, 330 struct gl_texture_object *texObj, 331 GLenum pname ) 332 { 333 radeonTexObj* t = radeon_tex_obj(texObj); 334 335 radeon_print(RADEON_TEXTURE, RADEON_VERBOSE, "%s( %s )\n", __func__, 336 _mesa_enum_to_string( pname ) ); 337 338 switch ( pname ) { 339 case GL_TEXTURE_BASE_LEVEL: 340 case GL_TEXTURE_MAX_LEVEL: 341 case GL_TEXTURE_MIN_LOD: 342 case GL_TEXTURE_MAX_LOD: 343 t->validated = GL_FALSE; 344 break; 345 346 default: 347 return; 348 } 349 } 350 351 static void radeonDeleteTexture( struct gl_context *ctx, 352 struct gl_texture_object *texObj ) 353 { 354 r100ContextPtr rmesa = R100_CONTEXT(ctx); 355 radeonTexObj* t = radeon_tex_obj(texObj); 356 int i; 357 358 radeon_print(RADEON_TEXTURE, RADEON_NORMAL, 359 "%s( %p (target = %s) )\n", __func__, (void *)texObj, 360 _mesa_enum_to_string( texObj->Target ) ); 361 362 if ( rmesa ) { 363 radeon_firevertices(&rmesa->radeon); 364 for ( i = 0 ; i < rmesa->radeon.glCtx.Const.MaxTextureUnits ; i++ ) { 365 if ( t == rmesa->state.texture.unit[i].texobj ) { 366 rmesa->state.texture.unit[i].texobj = NULL; 367 rmesa->hw.tex[i].dirty = GL_FALSE; 368 rmesa->hw.cube[i].dirty = GL_FALSE; 369 } 370 } 371 } 372 373 radeon_miptree_unreference(&t->mt); 374 375 /* Free mipmap images and the texture object itself */ 376 _mesa_delete_texture_object(ctx, texObj); 377 } 378 379 /* Need: 380 * - Same GEN_MODE for all active bits 381 * - Same EyePlane/ObjPlane for all active bits when using Eye/Obj 382 * - STRQ presumably all supported (matrix means incoming R values 383 * can end up in STQ, this has implications for vertex support, 384 * presumably ok if maos is used, though?) 385 * 386 * Basically impossible to do this on the fly - just collect some 387 * basic info & do the checks from ValidateState(). 388 */ 389 static void radeonTexGen( struct gl_context *ctx, 390 GLenum coord, 391 GLenum pname, 392 const GLfloat *params ) 393 { 394 r100ContextPtr rmesa = R100_CONTEXT(ctx); 395 GLuint unit = ctx->Texture.CurrentUnit; 396 rmesa->recheck_texgen[unit] = GL_TRUE; 397 } 398 399 /** 400 * Allocate a new texture object. 401 * Called via ctx->Driver.NewTextureObject. 402 * Note: we could use containment here to 'derive' the driver-specific 403 * texture object from the core mesa gl_texture_object. Not done at this time. 404 */ 405 static struct gl_texture_object * 406 radeonNewTextureObject( struct gl_context *ctx, GLuint name, GLenum target ) 407 { 408 r100ContextPtr rmesa = R100_CONTEXT(ctx); 409 radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj); 410 411 _mesa_initialize_texture_object(ctx, &t->base, name, target); 412 t->base.Sampler.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; 413 414 t->border_fallback = GL_FALSE; 415 416 t->pp_txfilter = RADEON_BORDER_MODE_OGL; 417 t->pp_txformat = (RADEON_TXFORMAT_ENDIAN_NO_SWAP | 418 RADEON_TXFORMAT_PERSPECTIVE_ENABLE); 419 420 radeonSetTexWrap( t, t->base.Sampler.WrapS, t->base.Sampler.WrapT ); 421 radeonSetTexMaxAnisotropy( t, t->base.Sampler.MaxAnisotropy ); 422 radeonSetTexFilter( t, t->base.Sampler.MinFilter, t->base.Sampler.MagFilter ); 423 radeonSetTexBorderColor( t, t->base.Sampler.BorderColor.f ); 424 return &t->base; 425 } 426 427 428 static struct gl_sampler_object * 429 radeonNewSamplerObject(struct gl_context *ctx, GLuint name) 430 { 431 r100ContextPtr rmesa = R100_CONTEXT(ctx); 432 struct gl_sampler_object *samp = _mesa_new_sampler_object(ctx, name); 433 if (samp) 434 samp->MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; 435 return samp; 436 } 437 438 439 void radeonInitTextureFuncs( radeonContextPtr radeon, struct dd_function_table *functions ) 440 { 441 radeon_init_common_texture_funcs(radeon, functions); 442 443 functions->NewTextureObject = radeonNewTextureObject; 444 // functions->BindTexture = radeonBindTexture; 445 functions->DeleteTexture = radeonDeleteTexture; 446 447 functions->TexEnv = radeonTexEnv; 448 functions->TexParameter = radeonTexParameter; 449 functions->TexGen = radeonTexGen; 450 functions->NewSamplerObject = radeonNewSamplerObject; 451 } 452
