1 /* Copyright 2014 The Chromium OS Authors. All rights reserved. 2 * Use of this source code is governed by a BSD-style license that can be 3 * found in the LICENSE file. 4 */ 5 6 #ifndef __CROS_EC_FLASH_LAYOUT_H 7 #define __CROS_EC_FLASH_LAYOUT_H 8 9 /* 10 * The flash memory is implemented in two halves. The SoC bootrom will look for 11 * a first-stage bootloader (aka "RO firmware") at the beginning of each of the 12 * two halves and prefer the newer one if both are valid. The chosen bootloader 13 * also looks in each half of the flash for a valid application image (("RW 14 * firmware"), so we have two possible RW images as well. The RO and RW images 15 * are not tightly coupled, so either RO image can choose to boot either RW 16 * image. RO images are provided by the SoC team, and can be updated separately 17 * from the RW images. 18 */ 19 20 /* Flash is directly addressable */ 21 #define CHIP_FLASH_BASE 0x40000 22 #define CHIP_FLASH_SIZE (512 * 1024) 23 #define CHIP_FLASH_HALF (CHIP_FLASH_SIZE >> 1) 24 25 /* Each half has to leave room for the image's signed header */ 26 #define CHIP_SIG_HEADER_SIZE 1024 27 28 /* This isn't optional, since the bootrom will always look for both */ 29 #define CHIP_HAS_RO_B 30 31 /* The RO images start at the very beginning of each flash half */ 32 #define CHIP_RO_A_MEM_OFF 0 33 #define CHIP_RO_B_MEM_OFF CHIP_FLASH_HALF 34 35 /* Size reserved for each RO image */ 36 #define CHIP_RO_SIZE 0x4000 37 38 /* 39 * RW images start right after the reserved-for-RO areas in each half, but only 40 * because that's where the RO images look for them. It's not a HW constraint. 41 */ 42 #define CHIP_RW_A_MEM_OFF CHIP_RO_SIZE 43 #define CHIP_RW_B_MEM_OFF (CHIP_FLASH_HALF + CHIP_RW_A_MEM_OFF) 44 45 /* 46 * Any reserved flash storage is placed after the RW image. It makes A/B 47 * updates MUCH simpler if both RW images are the same size, so we reserve the 48 * same amount in each half. 49 */ 50 #define CHIP_RW_SIZE \ 51 (CHIP_FLASH_HALF - CHIP_RW_A_MEM_OFF - CONFIG_FLASH_TOP_SIZE) 52 53 /* Reserved flash offset starts here. */ 54 #define CHIP_FLASH_TOP_A_OFF (CHIP_FLASH_HALF - CONFIG_FLASH_TOP_SIZE) 55 #define CHIP_FLASH_TOP_B_OFF (CHIP_FLASH_SIZE - CONFIG_FLASH_TOP_SIZE) 56 57 58 /* Internal flash specifics */ 59 #define CHIP_FLASH_BANK_SIZE 0x800 /* protect bank size */ 60 #define CHIP_FLASH_ERASE_SIZE 0x800 /* erase bank size */ 61 62 /* This flash can only be written as 4-byte words (aligned properly, too). */ 63 #define CHIP_FLASH_ERASED_VALUE32 0xffffffff 64 #define CHIP_FLASH_WRITE_SIZE 4 /* min write size (bytes) */ 65 66 /* But we have a 32-word buffer for writing multiple adjacent cells */ 67 #define CHIP_FLASH_WRITE_IDEAL_SIZE 128 /* best write size (bytes) */ 68 69 /* The flash controller prevents bulk writes that cross row boundaries */ 70 #define CHIP_FLASH_ROW_SIZE 256 /* row size */ 71 72 /* Manufacturing related data. */ 73 /* Certs in the RO region are written as 4-kB + 3-kB blocks to the A & 74 * B banks respectively. 75 */ 76 #define RO_CERTS_A_OFF (CHIP_RO_A_MEM_OFF + 0x2800) 77 #define RO_CERTS_B_OFF (CHIP_RO_B_MEM_OFF + 0x2800) 78 #define RO_CERTS_A_SIZE 0x01000 79 #define RO_CERTS_B_SIZE 0x00c00 80 /* We have an unused 3-kB region in the B bank, for future proofing. */ 81 #define RO_CERTS_PAD_B_SIZE 0x00c00 82 /* Factory provision data is written as a 2-kB block to the A bank. */ 83 #define RO_PROVISION_DATA_A_OFF 0x3800 84 #define RO_PROVISION_DATA_A_SIZE 0x0800 85 86 #endif /* __CROS_EC_FLASH_LAYOUT_H */ 87
