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      1 =pod
      2 
      3 =head1 NAME
      4 
      5 lli - directly execute programs from LLVM bitcode
      6 
      7 =head1 SYNOPSIS
      8 
      9 B<lli> [I<options>] [I<filename>] [I<program args>]
     10 
     11 =head1 DESCRIPTION
     12 
     13 B<lli> directly executes programs in LLVM bitcode format.  It takes a program
     14 in LLVM bitcode format and executes it using a just-in-time compiler, if one is
     15 available for the current architecture, or an interpreter.  B<lli> takes all of
     16 the same code generator options as L<llc|llc>, but they are only effective when
     17 B<lli> is using the just-in-time compiler.
     18 
     19 If I<filename> is not specified, then B<lli> reads the LLVM bitcode for the
     20 program from standard input.
     21 
     22 The optional I<args> specified on the command line are passed to the program as
     23 arguments.
     24 
     25 =head1 GENERAL OPTIONS
     26 
     27 =over
     28 
     29 =item B<-fake-argv0>=I<executable>
     30 
     31 Override the C<argv[0]> value passed into the executing program.
     32 
     33 =item B<-force-interpreter>=I<{false,true}>
     34 
     35 If set to true, use the interpreter even if a just-in-time compiler is available
     36 for this architecture. Defaults to false.
     37 
     38 =item B<-help>
     39 
     40 Print a summary of command line options.
     41 
     42 =item B<-load>=I<puginfilename>
     43 
     44 Causes B<lli> to load the plugin (shared object) named I<pluginfilename> and use
     45 it for optimization.
     46 
     47 =item B<-stats>
     48 
     49 Print statistics from the code-generation passes. This is only meaningful for
     50 the just-in-time compiler, at present.
     51 
     52 =item B<-time-passes>
     53 
     54 Record the amount of time needed for each code-generation pass and print it to
     55 standard error.
     56 
     57 =item B<-version>
     58 
     59 Print out the version of B<lli> and exit without doing anything else.
     60 
     61 =back 
     62 
     63 =head1 TARGET OPTIONS
     64 
     65 =over 
     66 
     67 =item B<-mtriple>=I<target triple>
     68 
     69 Override the target triple specified in the input bitcode file with the 
     70 specified string.  This may result in a crash if you pick an
     71 architecture which is not compatible with the current system.
     72 
     73 =item B<-march>=I<arch>
     74 
     75 Specify the architecture for which to generate assembly, overriding the target
     76 encoded in the bitcode file.  See the output of B<llc -help> for a list of
     77 valid architectures.  By default this is inferred from the target triple or
     78 autodetected to the current architecture.
     79 
     80 =item B<-mcpu>=I<cpuname>
     81 
     82 Specify a specific chip in the current architecture to generate code for.
     83 By default this is inferred from the target triple and autodetected to 
     84 the current architecture.  For a list of available CPUs, use:
     85 B<llvm-as E<lt> /dev/null | llc -march=xyz -mcpu=help>
     86 
     87 =item B<-mattr>=I<a1,+a2,-a3,...>
     88 
     89 Override or control specific attributes of the target, such as whether SIMD
     90 operations are enabled or not.  The default set of attributes is set by the
     91 current CPU.  For a list of available attributes, use:
     92 B<llvm-as E<lt> /dev/null | llc -march=xyz -mattr=help>
     93 
     94 =back
     95 
     96 
     97 =head1 FLOATING POINT OPTIONS
     98 
     99 =over 
    100 
    101 =item B<-disable-excess-fp-precision>
    102 
    103 Disable optimizations that may increase floating point precision.
    104 
    105 =item B<-enable-no-infs-fp-math>
    106 
    107 Enable optimizations that assume no Inf values.
    108 
    109 =item B<-enable-no-nans-fp-math>
    110 
    111 Enable optimizations that assume no NAN values.
    112 
    113 =item B<-enable-unsafe-fp-math>
    114 
    115 Causes B<lli> to enable optimizations that may decrease floating point
    116 precision.
    117 
    118 =item B<-soft-float>
    119 
    120 Causes B<lli> to generate software floating point library calls instead of
    121 equivalent hardware instructions.
    122 
    123 =back
    124 
    125 =head1 CODE GENERATION OPTIONS
    126 
    127 =over
    128 
    129 =item B<-code-model>=I<model>
    130 
    131 Choose the code model from:
    132 
    133     default: Target default code model
    134     small: Small code model
    135     kernel: Kernel code model
    136     medium: Medium code model
    137     large: Large code model
    138 
    139 =item B<-disable-post-RA-scheduler>
    140 
    141 Disable scheduling after register allocation.
    142 
    143 =item B<-disable-spill-fusing>
    144 
    145 Disable fusing of spill code into instructions.
    146 
    147 =item B<-enable-correct-eh-support> 
    148 
    149 Make the -lowerinvoke pass insert expensive, but correct, EH code.
    150 
    151 =item B<-jit-enable-eh> 
    152 
    153 Exception handling should be enabled in the just-in-time compiler.
    154 
    155 =item B<-join-liveintervals> 
    156 
    157 Coalesce copies (default=true).
    158 
    159 =item B<-nozero-initialized-in-bss>
    160 Don't place zero-initialized symbols into the BSS section.
    161 
    162 =item B<-pre-RA-sched>=I<scheduler>
    163 
    164 Instruction schedulers available (before register allocation):
    165 
    166     =default: Best scheduler for the target 
    167     =none: No scheduling: breadth first sequencing 
    168     =simple: Simple two pass scheduling: minimize critical path and maximize processor utilization 
    169     =simple-noitin: Simple two pass scheduling: Same as simple except using generic latency 
    170     =list-burr: Bottom-up register reduction list scheduling 
    171     =list-tdrr: Top-down register reduction list scheduling 
    172     =list-td: Top-down list scheduler -print-machineinstrs - Print generated machine code
    173 
    174 =item B<-regalloc>=I<allocator>
    175 
    176 Register allocator to use (default=linearscan)
    177 
    178     =bigblock: Big-block register allocator 
    179     =linearscan: linear scan register allocator =local -   local register allocator 
    180     =simple: simple register allocator 
    181 
    182 =item B<-relocation-model>=I<model> 
    183 
    184 Choose relocation model from:
    185 
    186     =default: Target default relocation model 
    187     =static: Non-relocatable code =pic -   Fully relocatable, position independent code 
    188     =dynamic-no-pic: Relocatable external references, non-relocatable code 
    189 
    190 =item B<-spiller>
    191 
    192 Spiller to use (default=local) 
    193 
    194     =simple: simple spiller 
    195     =local: local spiller 
    196 
    197 =item B<-x86-asm-syntax>=I<syntax>
    198 
    199 Choose style of code to emit from X86 backend: 
    200 
    201     =att: Emit AT&T-style assembly 
    202     =intel: Emit Intel-style assembly
    203 
    204 =back
    205 
    206 =head1 EXIT STATUS
    207 
    208 If B<lli> fails to load the program, it will exit with an exit code of 1.
    209 Otherwise, it will return the exit code of the program it executes.
    210 
    211 =head1 SEE ALSO
    212 
    213 L<llc|llc>
    214 
    215 =head1 AUTHOR
    216 
    217 Maintained by the LLVM Team (L<http://llvm.org/>).
    218 
    219 =cut
    220