1 //===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 //===----------------------------------------------------------------------===// 14 // Target-independent interfaces which we are implementing 15 //===----------------------------------------------------------------------===// 16 17 include "llvm/Target/Target.td" 18 19 //===----------------------------------------------------------------------===// 20 // ARM Subtarget state. 21 // 22 23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", 24 "Thumb mode">; 25 26 def ModeNaCl : SubtargetFeature<"nacl-mode", "InNaClMode", "true", 27 "Native client mode">; 28 29 //===----------------------------------------------------------------------===// 30 // ARM Subtarget features. 31 // 32 33 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 34 "Enable VFP2 instructions">; 35 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", 36 "Enable VFP3 instructions", 37 [FeatureVFP2]>; 38 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 39 "Enable NEON instructions", 40 [FeatureVFP3]>; 41 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 42 "Enable Thumb2 instructions">; 43 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 44 "Does not support ARM mode execution">; 45 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 46 "Enable half-precision floating point">; 47 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", 48 "Restrict VFP3 to 16 double registers">; 49 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true", 50 "Enable divide instructions">; 51 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true", 52 "Enable Thumb2 extract and pack instructions">; 53 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 54 "Has data barrier (dmb / dsb) instructions">; 55 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 56 "FP compare + branch is slow">; 57 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", 58 "Floating point unit supports single precision only">; 59 60 // Some processors have FP multiply-accumulate instructions that don't 61 // play nicely with other VFP / NEON instructions, and it's generally better 62 // to just not use them. 63 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 64 "Disable VFP / NEON MAC instructions">; 65 66 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 67 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 68 "HasVMLxForwarding", "true", 69 "Has multiplier accumulator forwarding">; 70 71 // Some processors benefit from using NEON instructions for scalar 72 // single-precision FP operations. 73 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", 74 "true", 75 "Use NEON for single precision FP">; 76 77 // Disable 32-bit to 16-bit narrowing for experimentation. 78 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 79 "Prefer 32-bit Thumb instrs">; 80 81 /// Some instructions update CPSR partially, which can add false dependency for 82 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 83 /// mapped to a separate physical register. Avoid partial CPSR update for these 84 /// processors. 85 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 86 "AvoidCPSRPartialUpdate", "true", 87 "Avoid CPSR partial update for OOO execution">; 88 89 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M) 90 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true", 91 "Supports v7 DSP instructions in Thumb2">; 92 93 // Multiprocessing extension. 94 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 95 "Supports Multiprocessing extension">; 96 97 // M-series ISA? 98 def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true", 99 "Is microcontroller profile ('M' series)">; 100 101 // ARM ISAs. 102 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 103 "Support ARM v4T instructions">; 104 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 105 "Support ARM v5T instructions", 106 [HasV4TOps]>; 107 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 108 "Support ARM v5TE, v5TEj, and v5TExp instructions", 109 [HasV5TOps]>; 110 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 111 "Support ARM v6 instructions", 112 [HasV5TEOps]>; 113 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 114 "Support ARM v6t2 instructions", 115 [HasV6Ops, FeatureThumb2]>; 116 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 117 "Support ARM v7 instructions", 118 [HasV6T2Ops]>; 119 120 //===----------------------------------------------------------------------===// 121 // ARM Processors supported. 122 // 123 124 include "ARMSchedule.td" 125 126 // ARM processor families. 127 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 128 "Cortex-A8 ARM processors", 129 [FeatureSlowFPBrcc, FeatureNEONForFP, 130 FeatureHasSlowFPVMLx, FeatureVMLxForwarding, 131 FeatureT2XtPk]>; 132 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 133 "Cortex-A9 ARM processors", 134 [FeatureVMLxForwarding, 135 FeatureT2XtPk, FeatureFP16, 136 FeatureAvoidPartialCPSR]>; 137 138 class ProcNoItin<string Name, list<SubtargetFeature> Features> 139 : Processor<Name, GenericItineraries, Features>; 140 141 // V4 Processors. 142 def : ProcNoItin<"generic", []>; 143 def : ProcNoItin<"arm8", []>; 144 def : ProcNoItin<"arm810", []>; 145 def : ProcNoItin<"strongarm", []>; 146 def : ProcNoItin<"strongarm110", []>; 147 def : ProcNoItin<"strongarm1100", []>; 148 def : ProcNoItin<"strongarm1110", []>; 149 150 // V4T Processors. 151 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>; 152 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>; 153 def : ProcNoItin<"arm710t", [HasV4TOps]>; 154 def : ProcNoItin<"arm720t", [HasV4TOps]>; 155 def : ProcNoItin<"arm9", [HasV4TOps]>; 156 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>; 157 def : ProcNoItin<"arm920", [HasV4TOps]>; 158 def : ProcNoItin<"arm920t", [HasV4TOps]>; 159 def : ProcNoItin<"arm922t", [HasV4TOps]>; 160 def : ProcNoItin<"arm940t", [HasV4TOps]>; 161 def : ProcNoItin<"ep9312", [HasV4TOps]>; 162 163 // V5T Processors. 164 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>; 165 def : ProcNoItin<"arm1020t", [HasV5TOps]>; 166 167 // V5TE Processors. 168 def : ProcNoItin<"arm9e", [HasV5TEOps]>; 169 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>; 170 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>; 171 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>; 172 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>; 173 def : ProcNoItin<"arm10e", [HasV5TEOps]>; 174 def : ProcNoItin<"arm1020e", [HasV5TEOps]>; 175 def : ProcNoItin<"arm1022e", [HasV5TEOps]>; 176 def : ProcNoItin<"xscale", [HasV5TEOps]>; 177 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>; 178 179 // V6 Processors. 180 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>; 181 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, 182 FeatureHasSlowFPVMLx]>; 183 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>; 184 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, 185 FeatureHasSlowFPVMLx]>; 186 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>; 187 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, 188 FeatureHasSlowFPVMLx]>; 189 190 // V6M Processors. 191 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM, 192 FeatureDB, FeatureMClass]>; 193 194 // V6T2 Processors. 195 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops, 196 FeatureDSPThumb2]>; 197 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2, 198 FeatureHasSlowFPVMLx, 199 FeatureDSPThumb2]>; 200 201 // V7a Processors. 202 def : Processor<"cortex-a8", CortexA8Itineraries, 203 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB, 204 FeatureDSPThumb2]>; 205 def : Processor<"cortex-a9", CortexA9Itineraries, 206 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, 207 FeatureDSPThumb2]>; 208 def : Processor<"cortex-a9-mp", CortexA9Itineraries, 209 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, 210 FeatureDSPThumb2, FeatureMP]>; 211 212 // V7M Processors. 213 def : ProcNoItin<"cortex-m3", [HasV7Ops, 214 FeatureThumb2, FeatureNoARM, FeatureDB, 215 FeatureHWDiv, FeatureMClass]>; 216 217 // V7EM Processors. 218 def : ProcNoItin<"cortex-m4", [HasV7Ops, 219 FeatureThumb2, FeatureNoARM, FeatureDB, 220 FeatureHWDiv, FeatureDSPThumb2, 221 FeatureT2XtPk, FeatureVFP2, 222 FeatureVFPOnlySP, FeatureMClass]>; 223 224 //===----------------------------------------------------------------------===// 225 // Register File Description 226 //===----------------------------------------------------------------------===// 227 228 include "ARMRegisterInfo.td" 229 230 include "ARMCallingConv.td" 231 232 //===----------------------------------------------------------------------===// 233 // Instruction Descriptions 234 //===----------------------------------------------------------------------===// 235 236 include "ARMInstrInfo.td" 237 238 def ARMInstrInfo : InstrInfo; 239 240 241 //===----------------------------------------------------------------------===// 242 // Assembly printer 243 //===----------------------------------------------------------------------===// 244 // ARM Uses the MC printer for asm output, so make sure the TableGen 245 // AsmWriter bits get associated with the correct class. 246 def ARMAsmWriter : AsmWriter { 247 string AsmWriterClassName = "InstPrinter"; 248 bit isMCAsmWriter = 1; 249 } 250 251 //===----------------------------------------------------------------------===// 252 // Declare the target which we are implementing 253 //===----------------------------------------------------------------------===// 254 255 def ARM : Target { 256 // Pull in Instruction Info: 257 let InstructionSet = ARMInstrInfo; 258 259 let AssemblyWriters = [ARMAsmWriter]; 260 } 261
