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      1 //===- MBlaze.td - Describe the MBlaze Target Machine ------*- tablegen -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 // This is the top level entry point for the MBlaze target.
     10 //===----------------------------------------------------------------------===//
     11 
     12 //===----------------------------------------------------------------------===//
     13 // Target-independent interfaces
     14 //===----------------------------------------------------------------------===//
     15 
     16 include "llvm/Target/Target.td"
     17 
     18 //===----------------------------------------------------------------------===//
     19 // Register File, Calling Conv, Instruction Descriptions
     20 //===----------------------------------------------------------------------===//
     21 
     22 include "MBlazeRegisterInfo.td"
     23 include "MBlazeSchedule.td"
     24 include "MBlazeIntrinsics.td"
     25 include "MBlazeInstrInfo.td"
     26 include "MBlazeCallingConv.td"
     27 
     28 def MBlazeInstrInfo : InstrInfo;
     29 
     30 //===----------------------------------------------------------------------===//
     31 // Microblaze Subtarget features                                              //
     32 //===----------------------------------------------------------------------===//
     33 
     34 def FeatureBarrel      : SubtargetFeature<"barrel", "HasBarrel", "true",
     35                                 "Implements barrel shifter">;
     36 def FeatureDiv         : SubtargetFeature<"div", "HasDiv", "true",
     37                                 "Implements hardware divider">;
     38 def FeatureMul         : SubtargetFeature<"mul", "HasMul", "true",
     39                                 "Implements hardware multiplier">;
     40 def FeaturePatCmp      : SubtargetFeature<"patcmp", "HasPatCmp", "true",
     41                                 "Implements pattern compare instruction">;
     42 def FeatureFPU         : SubtargetFeature<"fpu", "HasFPU", "true",
     43                                 "Implements floating point unit">;
     44 def FeatureMul64       : SubtargetFeature<"mul64", "HasMul64", "true",
     45                                 "Implements multiplier with 64-bit result">;
     46 def FeatureSqrt        : SubtargetFeature<"sqrt", "HasSqrt", "true",
     47                                 "Implements sqrt and floating point convert">;
     48 
     49 //===----------------------------------------------------------------------===//
     50 // MBlaze processors supported.
     51 //===----------------------------------------------------------------------===//
     52 
     53 def : Processor<"mblaze",  MBlazeGenericItineraries, []>;
     54 def : Processor<"mblaze3", MBlazePipe3Itineraries, []>;
     55 def : Processor<"mblaze5", MBlazePipe5Itineraries, []>;
     56 
     57 //===----------------------------------------------------------------------===//
     58 // Instruction Descriptions
     59 //===----------------------------------------------------------------------===//
     60 
     61 def MBlazeAsmWriter : AsmWriter {
     62   string AsmWriterClassName  = "InstPrinter";
     63   bit isMCAsmWriter = 1;
     64 }
     65 
     66 //===----------------------------------------------------------------------===//
     67 // Target Declaration
     68 //===----------------------------------------------------------------------===//
     69 
     70 def MBlaze : Target {
     71   let InstructionSet = MBlazeInstrInfo;
     72   let AssemblyWriters = [MBlazeAsmWriter];
     73 }
     74