1 //===-- MipsBaseInfo.h - Top level definitions for ARM ------- --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains small standalone helper functions and enum definitions for 11 // the Mips target useful for the compiler back-end and the MC libraries. 12 // 13 //===----------------------------------------------------------------------===// 14 #ifndef MIPSBASEINFO_H 15 #define MIPSBASEINFO_H 16 17 #include "MipsMCTargetDesc.h" 18 #include "llvm/Support/DataTypes.h" 19 #include "llvm/Support/ErrorHandling.h" 20 21 namespace llvm { 22 /// getMipsRegisterNumbering - Given the enum value for some register, 23 /// return the number that it corresponds to. 24 inline static unsigned getMipsRegisterNumbering(unsigned RegEnum) 25 { 26 switch (RegEnum) { 27 case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64: 28 case Mips::D0: 29 return 0; 30 case Mips::AT: case Mips::AT_64: case Mips::F1: case Mips::D1_64: 31 return 1; 32 case Mips::V0: case Mips::V0_64: case Mips::F2: case Mips::D2_64: 33 case Mips::D1: 34 return 2; 35 case Mips::V1: case Mips::V1_64: case Mips::F3: case Mips::D3_64: 36 return 3; 37 case Mips::A0: case Mips::A0_64: case Mips::F4: case Mips::D4_64: 38 case Mips::D2: 39 return 4; 40 case Mips::A1: case Mips::A1_64: case Mips::F5: case Mips::D5_64: 41 return 5; 42 case Mips::A2: case Mips::A2_64: case Mips::F6: case Mips::D6_64: 43 case Mips::D3: 44 return 6; 45 case Mips::A3: case Mips::A3_64: case Mips::F7: case Mips::D7_64: 46 return 7; 47 case Mips::T0: case Mips::T0_64: case Mips::F8: case Mips::D8_64: 48 case Mips::D4: 49 return 8; 50 case Mips::T1: case Mips::T1_64: case Mips::F9: case Mips::D9_64: 51 return 9; 52 case Mips::T2: case Mips::T2_64: case Mips::F10: case Mips::D10_64: 53 case Mips::D5: 54 return 10; 55 case Mips::T3: case Mips::T3_64: case Mips::F11: case Mips::D11_64: 56 return 11; 57 case Mips::T4: case Mips::T4_64: case Mips::F12: case Mips::D12_64: 58 case Mips::D6: 59 return 12; 60 case Mips::T5: case Mips::T5_64: case Mips::F13: case Mips::D13_64: 61 return 13; 62 case Mips::T6: case Mips::T6_64: case Mips::F14: case Mips::D14_64: 63 case Mips::D7: 64 return 14; 65 case Mips::T7: case Mips::T7_64: case Mips::F15: case Mips::D15_64: 66 return 15; 67 case Mips::S0: case Mips::S0_64: case Mips::F16: case Mips::D16_64: 68 case Mips::D8: 69 return 16; 70 case Mips::S1: case Mips::S1_64: case Mips::F17: case Mips::D17_64: 71 return 17; 72 case Mips::S2: case Mips::S2_64: case Mips::F18: case Mips::D18_64: 73 case Mips::D9: 74 return 18; 75 case Mips::S3: case Mips::S3_64: case Mips::F19: case Mips::D19_64: 76 return 19; 77 case Mips::S4: case Mips::S4_64: case Mips::F20: case Mips::D20_64: 78 case Mips::D10: 79 return 20; 80 case Mips::S5: case Mips::S5_64: case Mips::F21: case Mips::D21_64: 81 return 21; 82 case Mips::S6: case Mips::S6_64: case Mips::F22: case Mips::D22_64: 83 case Mips::D11: 84 return 22; 85 case Mips::S7: case Mips::S7_64: case Mips::F23: case Mips::D23_64: 86 return 23; 87 case Mips::T8: case Mips::T8_64: case Mips::F24: case Mips::D24_64: 88 case Mips::D12: 89 return 24; 90 case Mips::T9: case Mips::T9_64: case Mips::F25: case Mips::D25_64: 91 return 25; 92 case Mips::K0: case Mips::K0_64: case Mips::F26: case Mips::D26_64: 93 case Mips::D13: 94 return 26; 95 case Mips::K1: case Mips::K1_64: case Mips::F27: case Mips::D27_64: 96 return 27; 97 case Mips::GP: case Mips::GP_64: case Mips::F28: case Mips::D28_64: 98 case Mips::D14: 99 return 28; 100 case Mips::SP: case Mips::SP_64: case Mips::F29: case Mips::D29_64: 101 return 29; 102 case Mips::FP: case Mips::FP_64: case Mips::F30: case Mips::D30_64: 103 case Mips::D15: 104 return 30; 105 case Mips::RA: case Mips::RA_64: case Mips::F31: case Mips::D31_64: 106 return 31; 107 default: llvm_unreachable("Unknown register number!"); 108 } 109 return 0; // Not reached 110 } 111 } 112 113 #endif 114
