1 //===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the PowerPC 64-bit instructions. These patterns are used 11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // 64-bit operands. 17 // 18 def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 } 21 def u16imm64 : Operand<i64> { 22 let PrintMethod = "printU16ImmOperand"; 23 } 24 def symbolHi64 : Operand<i64> { 25 let PrintMethod = "printSymbolHi"; 26 let EncoderMethod = "getHA16Encoding"; 27 } 28 def symbolLo64 : Operand<i64> { 29 let PrintMethod = "printSymbolLo"; 30 let EncoderMethod = "getLO16Encoding"; 31 } 32 33 //===----------------------------------------------------------------------===// 34 // 64-bit transformation functions. 35 // 36 37 def SHL64 : SDNodeXForm<imm, [{ 38 // Transformation function: 63 - imm 39 return getI32Imm(63 - N->getZExtValue()); 40 }]>; 41 42 def SRL64 : SDNodeXForm<imm, [{ 43 // Transformation function: 64 - imm 44 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 45 }]>; 46 47 def HI32_48 : SDNodeXForm<imm, [{ 48 // Transformation function: shift the immediate value down into the low bits. 49 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 50 }]>; 51 52 def HI48_64 : SDNodeXForm<imm, [{ 53 // Transformation function: shift the immediate value down into the low bits. 54 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 55 }]>; 56 57 58 //===----------------------------------------------------------------------===// 59 // Calls. 60 // 61 62 let Defs = [LR8] in 63 def MovePCtoLR8 : Pseudo<(outs), (ins), "", []>, 64 PPC970_Unit_BRU; 65 66 // Darwin ABI Calls. 67 let isCall = 1, PPC970_Unit = 7, 68 // All calls clobber the PPC64 non-callee saved registers. 69 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12, 70 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 71 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 72 LR8,CTR8, 73 CR0,CR1,CR5,CR6,CR7,CARRY] in { 74 // Convenient aliases for call instructions 75 let Uses = [RM] in { 76 def BL8_Darwin : IForm<18, 0, 1, 77 (outs), (ins calltarget:$func, variable_ops), 78 "bl $func", BrB, []>; // See Pat patterns below. 79 def BLA8_Darwin : IForm<18, 1, 1, 80 (outs), (ins aaddr:$func, variable_ops), 81 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>; 82 } 83 let Uses = [CTR8, RM] in { 84 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 85 (outs), (ins variable_ops), 86 "bctrl", BrB, 87 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>; 88 } 89 } 90 91 // ELF 64 ABI Calls = Darwin ABI Calls 92 // Used to define BL8_ELF and BLA8_ELF 93 let isCall = 1, PPC970_Unit = 7, 94 // All calls clobber the PPC64 non-callee saved registers. 95 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12, 96 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 97 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 98 LR8,CTR8, 99 CR0,CR1,CR5,CR6,CR7,CARRY] in { 100 // Convenient aliases for call instructions 101 let Uses = [RM] in { 102 def BL8_ELF : IForm<18, 0, 1, 103 (outs), (ins calltarget:$func, variable_ops), 104 "bl $func", BrB, []>; // See Pat patterns below. 105 def BLA8_ELF : IForm<18, 1, 1, 106 (outs), (ins aaddr:$func, variable_ops), 107 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>; 108 } 109 let Uses = [CTR8, RM] in { 110 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1, 111 (outs), (ins variable_ops), 112 "bctrl", BrB, 113 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>; 114 } 115 } 116 117 118 // Calls 119 def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)), 120 (BL8_Darwin tglobaladdr:$dst)>; 121 def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)), 122 (BL8_Darwin texternalsym:$dst)>; 123 124 def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)), 125 (BL8_ELF tglobaladdr:$dst)>; 126 def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)), 127 (BL8_ELF texternalsym:$dst)>; 128 def : Pat<(PPCnop), 129 (NOP)>; 130 131 // Atomic operations 132 let usesCustomInserter = 1 in { 133 let Defs = [CR0] in { 134 def ATOMIC_LOAD_ADD_I64 : Pseudo< 135 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 136 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>; 137 def ATOMIC_LOAD_SUB_I64 : Pseudo< 138 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 139 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>; 140 def ATOMIC_LOAD_OR_I64 : Pseudo< 141 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 142 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>; 143 def ATOMIC_LOAD_XOR_I64 : Pseudo< 144 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 145 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>; 146 def ATOMIC_LOAD_AND_I64 : Pseudo< 147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 148 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>; 149 def ATOMIC_LOAD_NAND_I64 : Pseudo< 150 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 151 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>; 152 153 def ATOMIC_CMP_SWAP_I64 : Pseudo< 154 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "", 155 [(set G8RC:$dst, 156 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>; 157 158 def ATOMIC_SWAP_I64 : Pseudo< 159 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "", 160 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>; 161 } 162 } 163 164 // Instructions to support atomic operations 165 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), 166 "ldarx $rD, $ptr", LdStLDARX, 167 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; 168 169 let Defs = [CR0] in 170 def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), 171 "stdcx. $rS, $dst", LdStSTDCX, 172 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, 173 isDOT; 174 175 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 176 def TCRETURNdi8 :Pseudo< (outs), 177 (ins calltarget:$dst, i32imm:$offset, variable_ops), 178 "#TC_RETURNd8 $dst $offset", 179 []>; 180 181 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 182 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops), 183 "#TC_RETURNa8 $func $offset", 184 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 185 186 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 187 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset, variable_ops), 188 "#TC_RETURNr8 $dst $offset", 189 []>; 190 191 192 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 193 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in { 194 let isReturn = 1 in { 195 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 196 Requires<[In64BitMode]>; 197 } 198 199 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 200 Requires<[In64BitMode]>; 201 } 202 203 204 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 205 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 206 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 207 "b $dst", BrB, 208 []>; 209 210 211 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 212 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 213 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 214 "ba $dst", BrB, 215 []>; 216 217 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 218 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 219 220 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 221 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 222 223 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 224 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 225 226 227 //===----------------------------------------------------------------------===// 228 // 64-bit SPR manipulation instrs. 229 230 let Uses = [CTR8] in { 231 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins), 232 "mfctr $rT", SprMFSPR>, 233 PPC970_DGroup_First, PPC970_Unit_FXU; 234 } 235 let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in { 236 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS), 237 "mtctr $rS", SprMTSPR>, 238 PPC970_DGroup_First, PPC970_Unit_FXU; 239 } 240 241 let Defs = [X1], Uses = [X1] in 242 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"", 243 [(set G8RC:$result, 244 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>; 245 246 let Defs = [LR8] in { 247 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS), 248 "mtlr $rS", SprMTSPR>, 249 PPC970_DGroup_First, PPC970_Unit_FXU; 250 } 251 let Uses = [LR8] in { 252 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins), 253 "mflr $rT", SprMFSPR>, 254 PPC970_DGroup_First, PPC970_Unit_FXU; 255 } 256 257 //===----------------------------------------------------------------------===// 258 // Fixed point instructions. 259 // 260 261 let PPC970_Unit = 1 in { // FXU Operations. 262 263 // Copies, extends, truncates. 264 def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB), 265 "or $rA, $rS, $rB", IntGeneral, 266 []>; 267 def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB), 268 "or $rA, $rS, $rB", IntGeneral, 269 []>; 270 271 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), 272 "li $rD, $imm", IntGeneral, 273 [(set G8RC:$rD, immSExt16:$imm)]>; 274 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), 275 "lis $rD, $imm", IntGeneral, 276 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 277 278 // Logical ops. 279 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 280 "nand $rA, $rS, $rB", IntGeneral, 281 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; 282 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 283 "and $rA, $rS, $rB", IntGeneral, 284 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; 285 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 286 "andc $rA, $rS, $rB", IntGeneral, 287 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; 288 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 289 "or $rA, $rS, $rB", IntGeneral, 290 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 291 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 292 "nor $rA, $rS, $rB", IntGeneral, 293 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; 294 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 295 "orc $rA, $rS, $rB", IntGeneral, 296 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; 297 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 298 "eqv $rA, $rS, $rB", IntGeneral, 299 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; 300 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 301 "xor $rA, $rS, $rB", IntGeneral, 302 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; 303 304 // Logical ops with immediate. 305 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 306 "andi. $dst, $src1, $src2", IntGeneral, 307 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, 308 isDOT; 309 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 310 "andis. $dst, $src1, $src2", IntGeneral, 311 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, 312 isDOT; 313 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 314 "ori $dst, $src1, $src2", IntGeneral, 315 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; 316 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 317 "oris $dst, $src1, $src2", IntGeneral, 318 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; 319 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 320 "xori $dst, $src1, $src2", IntGeneral, 321 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; 322 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 323 "xoris $dst, $src1, $src2", IntGeneral, 324 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; 325 326 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 327 "add $rT, $rA, $rB", IntGeneral, 328 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 329 330 let Defs = [CARRY] in { 331 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 332 "addc $rT, $rA, $rB", IntGeneral, 333 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>, 334 PPC970_DGroup_Cracked; 335 def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 336 "addic $rD, $rA, $imm", IntGeneral, 337 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>; 338 } 339 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 340 "addi $rD, $rA, $imm", IntGeneral, 341 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 342 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm), 343 "addis $rD, $rA, $imm", IntGeneral, 344 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; 345 346 let Defs = [CARRY] in { 347 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 348 "subfic $rD, $rA, $imm", IntGeneral, 349 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; 350 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 351 "subfc $rT, $rA, $rB", IntGeneral, 352 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>, 353 PPC970_DGroup_Cracked; 354 } 355 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 356 "subf $rT, $rA, $rB", IntGeneral, 357 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; 358 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA), 359 "neg $rT, $rA", IntGeneral, 360 [(set G8RC:$rT, (ineg G8RC:$rA))]>; 361 let Uses = [CARRY], Defs = [CARRY] in { 362 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 363 "adde $rT, $rA, $rB", IntGeneral, 364 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>; 365 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA), 366 "addme $rT, $rA", IntGeneral, 367 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>; 368 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA), 369 "addze $rT, $rA", IntGeneral, 370 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>; 371 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 372 "subfe $rT, $rA, $rB", IntGeneral, 373 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>; 374 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA), 375 "subfme $rT, $rA", IntGeneral, 376 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>; 377 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA), 378 "subfze $rT, $rA", IntGeneral, 379 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>; 380 } 381 382 383 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 384 "mulhd $rT, $rA, $rB", IntMulHW, 385 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 386 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 387 "mulhdu $rT, $rA, $rB", IntMulHWU, 388 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 389 390 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 391 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 392 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 393 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 394 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm), 395 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 396 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2), 397 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 398 399 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 400 "sld $rA, $rS, $rB", IntRotateD, 401 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64; 402 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 403 "srd $rA, $rS, $rB", IntRotateD, 404 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64; 405 let Defs = [CARRY] in { 406 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 407 "srad $rA, $rS, $rB", IntRotateD, 408 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64; 409 } 410 411 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), 412 "extsb $rA, $rS", IntGeneral, 413 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>; 414 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS), 415 "extsh $rA, $rS", IntGeneral, 416 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>; 417 418 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS), 419 "extsw $rA, $rS", IntGeneral, 420 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 421 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 422 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS), 423 "extsw $rA, $rS", IntGeneral, 424 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 425 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS), 426 "extsw $rA, $rS", IntGeneral, 427 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64; 428 429 let Defs = [CARRY] in { 430 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH), 431 "sradi $rA, $rS, $SH", IntRotateD, 432 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; 433 } 434 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS), 435 "cntlzd $rA, $rS", IntGeneral, 436 [(set G8RC:$rA, (ctlz G8RC:$rS))]>; 437 438 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 439 "divd $rT, $rA, $rB", IntDivD, 440 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 441 PPC970_DGroup_First, PPC970_DGroup_Cracked; 442 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 443 "divdu $rT, $rA, $rB", IntDivD, 444 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 445 PPC970_DGroup_First, PPC970_DGroup_Cracked; 446 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 447 "mulld $rT, $rA, $rB", IntMulHD, 448 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 449 450 451 let isCommutable = 1 in { 452 def RLDIMI : MDForm_1<30, 3, 453 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 454 "rldimi $rA, $rS, $SH, $MB", IntRotateD, 455 []>, isPPC64, RegConstraint<"$rSi = $rA">, 456 NoEncode<"$rSi">; 457 } 458 459 // Rotate instructions. 460 def RLDCL : MDForm_1<30, 0, 461 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB), 462 "rldcl $rA, $rS, $rB, $MB", IntRotateD, 463 []>, isPPC64; 464 def RLDICL : MDForm_1<30, 0, 465 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB), 466 "rldicl $rA, $rS, $SH, $MB", IntRotateD, 467 []>, isPPC64; 468 def RLDICR : MDForm_1<30, 1, 469 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME), 470 "rldicr $rA, $rS, $SH, $ME", IntRotateD, 471 []>, isPPC64; 472 } // End FXU Operations. 473 474 475 //===----------------------------------------------------------------------===// 476 // Load/Store instructions. 477 // 478 479 480 // Sign extending loads. 481 let canFoldAsLoad = 1, PPC970_Unit = 2 in { 482 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), 483 "lha $rD, $src", LdStLHA, 484 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, 485 PPC970_DGroup_Cracked; 486 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src), 487 "lwa $rD, $src", LdStLWA, 488 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64, 489 PPC970_DGroup_Cracked; 490 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src), 491 "lhax $rD, $src", LdStLHA, 492 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, 493 PPC970_DGroup_Cracked; 494 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), 495 "lwax $rD, $src", LdStLHA, 496 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 497 PPC970_DGroup_Cracked; 498 499 // Update forms. 500 let mayLoad = 1 in 501 def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp, 502 ptr_rc:$rA), 503 "lhau $rD, $disp($rA)", LdStGeneral, 504 []>, RegConstraint<"$rA = $ea_result">, 505 NoEncode<"$ea_result">; 506 // NO LWAU! 507 508 } 509 510 // Zero extending loads. 511 let canFoldAsLoad = 1, PPC970_Unit = 2 in { 512 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), 513 "lbz $rD, $src", LdStGeneral, 514 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; 515 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src), 516 "lhz $rD, $src", LdStGeneral, 517 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; 518 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src), 519 "lwz $rD, $src", LdStGeneral, 520 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 521 522 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src), 523 "lbzx $rD, $src", LdStGeneral, 524 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; 525 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src), 526 "lhzx $rD, $src", LdStGeneral, 527 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; 528 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), 529 "lwzx $rD, $src", LdStGeneral, 530 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; 531 532 533 // Update forms. 534 let mayLoad = 1 in { 535 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 536 "lbzu $rD, $addr", LdStGeneral, 537 []>, RegConstraint<"$addr.reg = $ea_result">, 538 NoEncode<"$ea_result">; 539 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 540 "lhzu $rD, $addr", LdStGeneral, 541 []>, RegConstraint<"$addr.reg = $ea_result">, 542 NoEncode<"$ea_result">; 543 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 544 "lwzu $rD, $addr", LdStGeneral, 545 []>, RegConstraint<"$addr.reg = $ea_result">, 546 NoEncode<"$ea_result">; 547 } 548 } 549 550 551 // Full 8-byte loads. 552 let canFoldAsLoad = 1, PPC970_Unit = 2 in { 553 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), 554 "ld $rD, $src", LdStLD, 555 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; 556 def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 557 "", 558 [(set G8RC:$rD, 559 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 560 561 let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo. 562 def LDinto_toc: DSForm_1<58, 0, (outs), (ins G8RC:$reg), 563 "ld 2, 8($reg)", LdStLD, 564 [(PPCload_toc G8RC:$reg)]>, isPPC64; 565 566 let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo. 567 def LDtoc_restore : DSForm_1<58, 0, (outs), (ins), 568 "ld 2, 40(1)", LdStLD, 569 [(PPCtoc_restore)]>, isPPC64; 570 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), 571 "ldx $rD, $src", LdStLD, 572 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 573 574 let mayLoad = 1 in 575 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr), 576 "ldu $rD, $addr", LdStLD, 577 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 578 NoEncode<"$ea_result">; 579 580 } 581 582 def : Pat<(PPCload ixaddr:$src), 583 (LD ixaddr:$src)>; 584 def : Pat<(PPCload xaddr:$src), 585 (LDX xaddr:$src)>; 586 587 let PPC970_Unit = 2 in { 588 // Truncating stores. 589 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src), 590 "stb $rS, $src", LdStGeneral, 591 [(truncstorei8 G8RC:$rS, iaddr:$src)]>; 592 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src), 593 "sth $rS, $src", LdStGeneral, 594 [(truncstorei16 G8RC:$rS, iaddr:$src)]>; 595 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src), 596 "stw $rS, $src", LdStGeneral, 597 [(truncstorei32 G8RC:$rS, iaddr:$src)]>; 598 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst), 599 "stbx $rS, $dst", LdStGeneral, 600 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>, 601 PPC970_DGroup_Cracked; 602 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst), 603 "sthx $rS, $dst", LdStGeneral, 604 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>, 605 PPC970_DGroup_Cracked; 606 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst), 607 "stwx $rS, $dst", LdStGeneral, 608 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>, 609 PPC970_DGroup_Cracked; 610 // Normal 8-byte stores. 611 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst), 612 "std $rS, $dst", LdStSTD, 613 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64; 614 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst), 615 "stdx $rS, $dst", LdStSTD, 616 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64, 617 PPC970_DGroup_Cracked; 618 } 619 620 let PPC970_Unit = 2 in { 621 622 def STBU8 : DForm_1a<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 623 symbolLo:$ptroff, ptr_rc:$ptrreg), 624 "stbu $rS, $ptroff($ptrreg)", LdStGeneral, 625 [(set ptr_rc:$ea_res, 626 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, 627 iaddroff:$ptroff))]>, 628 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 629 def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 630 symbolLo:$ptroff, ptr_rc:$ptrreg), 631 "sthu $rS, $ptroff($ptrreg)", LdStGeneral, 632 [(set ptr_rc:$ea_res, 633 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, 634 iaddroff:$ptroff))]>, 635 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 636 637 def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 638 s16immX4:$ptroff, ptr_rc:$ptrreg), 639 "stdu $rS, $ptroff($ptrreg)", LdStSTD, 640 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, 641 iaddroff:$ptroff))]>, 642 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">, 643 isPPC64; 644 645 let mayStore = 1 in 646 def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst), 647 "stdux $rS, $dst", LdStSTD, 648 []>, isPPC64; 649 650 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 651 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), 652 "std $rT, $dst", LdStSTD, 653 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 654 def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst), 655 "stdx $rT, $dst", LdStSTD, 656 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 657 PPC970_DGroup_Cracked; 658 } 659 660 661 662 //===----------------------------------------------------------------------===// 663 // Floating point instructions. 664 // 665 666 667 let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations. 668 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB), 669 "fcfid $frD, $frB", FPGeneral, 670 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 671 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB), 672 "fctidz $frD, $frB", FPGeneral, 673 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 674 } 675 676 677 //===----------------------------------------------------------------------===// 678 // Instruction Patterns 679 // 680 681 // Extensions and truncates to/from 32-bit regs. 682 def : Pat<(i64 (zext GPRC:$in)), 683 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; 684 def : Pat<(i64 (anyext GPRC:$in)), 685 (OR4To8 GPRC:$in, GPRC:$in)>; 686 def : Pat<(i32 (trunc G8RC:$in)), 687 (OR8To4 G8RC:$in, G8RC:$in)>; 688 689 // Extending loads with i64 targets. 690 def : Pat<(zextloadi1 iaddr:$src), 691 (LBZ8 iaddr:$src)>; 692 def : Pat<(zextloadi1 xaddr:$src), 693 (LBZX8 xaddr:$src)>; 694 def : Pat<(extloadi1 iaddr:$src), 695 (LBZ8 iaddr:$src)>; 696 def : Pat<(extloadi1 xaddr:$src), 697 (LBZX8 xaddr:$src)>; 698 def : Pat<(extloadi8 iaddr:$src), 699 (LBZ8 iaddr:$src)>; 700 def : Pat<(extloadi8 xaddr:$src), 701 (LBZX8 xaddr:$src)>; 702 def : Pat<(extloadi16 iaddr:$src), 703 (LHZ8 iaddr:$src)>; 704 def : Pat<(extloadi16 xaddr:$src), 705 (LHZX8 xaddr:$src)>; 706 def : Pat<(extloadi32 iaddr:$src), 707 (LWZ8 iaddr:$src)>; 708 def : Pat<(extloadi32 xaddr:$src), 709 (LWZX8 xaddr:$src)>; 710 711 // Standard shifts. These are represented separately from the real shifts above 712 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift 713 // amounts. 714 def : Pat<(sra G8RC:$rS, GPRC:$rB), 715 (SRAD G8RC:$rS, GPRC:$rB)>; 716 def : Pat<(srl G8RC:$rS, GPRC:$rB), 717 (SRD G8RC:$rS, GPRC:$rB)>; 718 def : Pat<(shl G8RC:$rS, GPRC:$rB), 719 (SLD G8RC:$rS, GPRC:$rB)>; 720 721 // SHL/SRL 722 def : Pat<(shl G8RC:$in, (i32 imm:$imm)), 723 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 724 def : Pat<(srl G8RC:$in, (i32 imm:$imm)), 725 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 726 727 // ROTL 728 def : Pat<(rotl G8RC:$in, GPRC:$sh), 729 (RLDCL G8RC:$in, GPRC:$sh, 0)>; 730 def : Pat<(rotl G8RC:$in, (i32 imm:$imm)), 731 (RLDICL G8RC:$in, imm:$imm, 0)>; 732 733 // Hi and Lo for Darwin Global Addresses. 734 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 735 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 736 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 737 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 738 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 739 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 740 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 741 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 742 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)), 743 (ADDIS8 G8RC:$in, tglobaladdr:$g)>; 744 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)), 745 (ADDIS8 G8RC:$in, tconstpool:$g)>; 746 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)), 747 (ADDIS8 G8RC:$in, tjumptable:$g)>; 748 def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)), 749 (ADDIS8 G8RC:$in, tblockaddress:$g)>; 750
