1 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=FINITE %s 2 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math | FileCheck -check-prefix=NAN %s 3 ; rdar://7461510 4 5 define arm_apcscc i32 @t1(float* %a, float* %b) nounwind { 6 entry: 7 ; FINITE: t1: 8 ; FINITE-NOT: vldr 9 ; FINITE: ldr 10 ; FINITE: ldr 11 ; FINITE: cmp r0, r1 12 ; FINITE-NOT: vcmpe.f32 13 ; FINITE-NOT: vmrs 14 ; FINITE: beq 15 16 ; NAN: t1: 17 ; NAN: vldr.32 s0, 18 ; NAN: vldr.32 s1, 19 ; NAN: vcmpe.f32 s1, s0 20 ; NAN: vmrs apsr_nzcv, fpscr 21 ; NAN: beq 22 %0 = load float* %a 23 %1 = load float* %b 24 %2 = fcmp une float %0, %1 25 br i1 %2, label %bb1, label %bb2 26 27 bb1: 28 %3 = call i32 @bar() 29 ret i32 %3 30 31 bb2: 32 %4 = call i32 @foo() 33 ret i32 %4 34 } 35 36 define arm_apcscc i32 @t2(double* %a, double* %b) nounwind { 37 entry: 38 ; FINITE: t2: 39 ; FINITE-NOT: vldr 40 ; FINITE: ldrd r0, r1, [r0] 41 ; FINITE-NOT: b LBB 42 ; FINITE: cmp r0, #0 43 ; FINITE: cmpeq r1, #0 44 ; FINITE-NOT: vcmpe.f32 45 ; FINITE-NOT: vmrs 46 ; FINITE: bne 47 %0 = load double* %a 48 %1 = fcmp oeq double %0, 0.000000e+00 49 br i1 %1, label %bb1, label %bb2 50 51 bb1: 52 %2 = call i32 @bar() 53 ret i32 %2 54 55 bb2: 56 %3 = call i32 @foo() 57 ret i32 %3 58 } 59 60 define arm_apcscc i32 @t3(float* %a, float* %b) nounwind { 61 entry: 62 ; FINITE: t3: 63 ; FINITE-NOT: vldr 64 ; FINITE: ldr r0, [r0] 65 ; FINITE: cmp r0, #0 66 ; FINITE-NOT: vcmpe.f32 67 ; FINITE-NOT: vmrs 68 ; FINITE: bne 69 %0 = load float* %a 70 %1 = fcmp oeq float %0, 0.000000e+00 71 br i1 %1, label %bb1, label %bb2 72 73 bb1: 74 %2 = call i32 @bar() 75 ret i32 %2 76 77 bb2: 78 %3 = call i32 @foo() 79 ret i32 %3 80 } 81 82 declare i32 @bar() 83 declare i32 @foo() 84
