1 ; RUN: llc < %s -march=cellspu > %t1.s 2 ; RUN: grep xswd %t1.s | count 3 3 ; RUN: grep xsbh %t1.s | count 1 4 ; RUN: grep xshw %t1.s | count 2 5 ; RUN: grep shufb %t1.s | count 7 6 ; RUN: grep cg %t1.s | count 4 7 ; RUN: grep addx %t1.s | count 4 8 ; RUN: grep fsmbi %t1.s | count 3 9 ; RUN: grep il %t1.s | count 2 10 ; RUN: grep mpy %t1.s | count 10 11 ; RUN: grep mpyh %t1.s | count 6 12 ; RUN: grep mpyhhu %t1.s | count 2 13 ; RUN: grep mpyu %t1.s | count 4 14 15 ; ModuleID = 'stores.bc' 16 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" 17 target triple = "spu" 18 19 define i64 @sext_i64_i8(i8 %a) nounwind { 20 %1 = sext i8 %a to i64 21 ret i64 %1 22 } 23 24 define i64 @sext_i64_i16(i16 %a) nounwind { 25 %1 = sext i16 %a to i64 26 ret i64 %1 27 } 28 29 define i64 @sext_i64_i32(i32 %a) nounwind { 30 %1 = sext i32 %a to i64 31 ret i64 %1 32 } 33 34 define i64 @zext_i64_i8(i8 %a) nounwind { 35 %1 = zext i8 %a to i64 36 ret i64 %1 37 } 38 39 define i64 @zext_i64_i16(i16 %a) nounwind { 40 %1 = zext i16 %a to i64 41 ret i64 %1 42 } 43 44 define i64 @zext_i64_i32(i32 %a) nounwind { 45 %1 = zext i32 %a to i64 46 ret i64 %1 47 } 48 49 define i64 @add_i64(i64 %a, i64 %b) nounwind { 50 %1 = add i64 %a, %b 51 ret i64 %1 52 } 53 54 define i64 @mul_i64(i64 %a, i64 %b) nounwind { 55 %1 = mul i64 %a, %b 56 ret i64 %1 57 } 58
