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      1 ; RUN: llc < %s -march=cellspu > %t1.s
      2 ; RUN: grep ilhu  %t1.s | count 9
      3 ; RUN: grep iohl  %t1.s | count 7
      4 ; RUN: grep -w il    %t1.s | count 3
      5 ; RUN: grep 16429 %t1.s | count 1
      6 ; RUN: grep 63572 %t1.s | count 1
      7 ; RUN: grep   128 %t1.s | count 1
      8 ; RUN: grep 32639 %t1.s | count 1
      9 ; RUN: grep 65535 %t1.s | count 1
     10 ; RUN: grep 16457 %t1.s | count 1
     11 ; RUN: grep  4059 %t1.s | count 1
     12 ; RUN: grep 49077 %t1.s | count 1
     13 ; RUN: grep  1267 %t1.s | count 2
     14 ; RUN: grep 16309 %t1.s | count 1
     15 ; RUN: cat %t1.s | FileCheck %s
     16 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
     17 target triple = "spu"
     18 
     19 define i32 @test_1() {
     20   ret i32 4784128               ;; ILHU via pattern (0x49000)
     21 }
     22 
     23 define i32 @test_2() {
     24   ret i32 5308431               ;; ILHU/IOHL via pattern (0x5100f)
     25 }
     26 
     27 define i32 @test_3() {
     28   ret i32 511                   ;; IL via pattern
     29 }
     30 
     31 define i32 @test_4() {
     32   ret i32 -512                  ;; IL via pattern
     33 }
     34 
     35 define i32 @test_5()
     36 {
     37 ;CHECK: test_5:
     38 ;CHECK-NOT: ila $3, 40000
     39 ;CHECK: ilhu
     40 ;CHECK: iohl
     41 ;CHECK: bi $lr
     42   ret i32 400000
     43 }
     44 
     45 ;; double             float       floatval
     46 ;; 0x4005bf0a80000000 0x402d|f854 2.718282
     47 define float @float_const_1() {
     48   ret float 0x4005BF0A80000000  ;; ILHU/IOHL
     49 }
     50 
     51 ;; double             float       floatval
     52 ;; 0x3810000000000000 0x0080|0000 0.000000
     53 define float @float_const_2() {
     54   ret float 0x3810000000000000  ;; IL 128
     55 }
     56 
     57 ;; double             float       floatval
     58 ;; 0x47efffffe0000000 0x7f7f|ffff NaN
     59 define float @float_const_3() {
     60   ret float 0x47EFFFFFE0000000  ;; ILHU/IOHL via pattern
     61 }
     62 
     63 ;; double             float       floatval
     64 ;; 0x400921fb60000000 0x4049|0fdb 3.141593
     65 define float @float_const_4() {
     66   ret float 0x400921FB60000000  ;; ILHU/IOHL via pattern
     67 }
     68 
     69 ;; double             float       floatval
     70 ;; 0xbff6a09e60000000 0xbfb5|04f3 -1.414214
     71 define float @float_const_5() {
     72   ret float 0xBFF6A09E60000000  ;; ILHU/IOHL via pattern
     73 }
     74 
     75 ;; double             float       floatval
     76 ;; 0x3ff6a09e60000000 0x3fb5|04f3 1.414214
     77 define float @float_const_6() {
     78   ret float 0x3FF6A09E60000000  ;; ILHU/IOHL via pattern
     79 }
     80 
     81 define float @float_const_7() {
     82   ret float 0.000000e+00        ;; IL 0 via pattern
     83 }
     84