1 ; RUN: llc < %s -march=cellspu > %t1.s 2 ; RUN: grep fa %t1.s | count 5 3 ; RUN: grep fs %t1.s | count 5 4 ; RUN: grep fm %t1.s | count 15 5 ; RUN: grep fceq %t1.s | count 5 6 ; RUN: grep fcmeq %t1.s | count 5 7 ; RUN: grep fcgt %t1.s | count 5 8 ; RUN: grep fcmgt %t1.s | count 5 9 ; RUN: grep fma %t1.s | count 5 10 ; RUN: grep fnms %t1.s | count 5 11 ; RUN: grep fms %t1.s | count 5 12 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" 13 target triple = "spu" 14 15 declare <4 x i32> @llvm.spu.si.shli(<4 x i32>, i8) 16 17 declare <4 x float> @llvm.spu.si.fa(<4 x float>, <4 x float>) 18 declare <4 x float> @llvm.spu.si.fs(<4 x float>, <4 x float>) 19 declare <4 x float> @llvm.spu.si.fm(<4 x float>, <4 x float>) 20 21 declare <4 x float> @llvm.spu.si.fceq(<4 x float>, <4 x float>) 22 declare <4 x float> @llvm.spu.si.fcmeq(<4 x float>, <4 x float>) 23 declare <4 x float> @llvm.spu.si.fcgt(<4 x float>, <4 x float>) 24 declare <4 x float> @llvm.spu.si.fcmgt(<4 x float>, <4 x float>) 25 26 declare <4 x float> @llvm.spu.si.fma(<4 x float>, <4 x float>, <4 x float>) 27 declare <4 x float> @llvm.spu.si.fnms(<4 x float>, <4 x float>, <4 x float>) 28 declare <4 x float> @llvm.spu.si.fms(<4 x float>, <4 x float>, <4 x float>) 29 30 define <4 x i32> @test(<4 x i32> %A) { 31 call <4 x i32> @llvm.spu.si.shli(<4 x i32> %A, i8 3) 32 %Y = bitcast <4 x i32> %1 to <4 x i32> 33 ret <4 x i32> %Y 34 } 35 36 define <4 x float> @fatest(<4 x float> %A, <4 x float> %B) { 37 call <4 x float> @llvm.spu.si.fa(<4 x float> %A, <4 x float> %B) 38 %Y = bitcast <4 x float> %1 to <4 x float> 39 ret <4 x float> %Y 40 } 41 42 define <4 x float> @fstest(<4 x float> %A, <4 x float> %B) { 43 call <4 x float> @llvm.spu.si.fs(<4 x float> %A, <4 x float> %B) 44 %Y = bitcast <4 x float> %1 to <4 x float> 45 ret <4 x float> %Y 46 } 47 48 define <4 x float> @fmtest(<4 x float> %A, <4 x float> %B) { 49 call <4 x float> @llvm.spu.si.fm(<4 x float> %A, <4 x float> %B) 50 %Y = bitcast <4 x float> %1 to <4 x float> 51 ret <4 x float> %Y 52 } 53 54 define <4 x float> @fceqtest(<4 x float> %A, <4 x float> %B) { 55 call <4 x float> @llvm.spu.si.fceq(<4 x float> %A, <4 x float> %B) 56 %Y = bitcast <4 x float> %1 to <4 x float> 57 ret <4 x float> %Y 58 } 59 60 define <4 x float> @fcmeqtest(<4 x float> %A, <4 x float> %B) { 61 call <4 x float> @llvm.spu.si.fcmeq(<4 x float> %A, <4 x float> %B) 62 %Y = bitcast <4 x float> %1 to <4 x float> 63 ret <4 x float> %Y 64 } 65 66 define <4 x float> @fcgttest(<4 x float> %A, <4 x float> %B) { 67 call <4 x float> @llvm.spu.si.fcgt(<4 x float> %A, <4 x float> %B) 68 %Y = bitcast <4 x float> %1 to <4 x float> 69 ret <4 x float> %Y 70 } 71 72 define <4 x float> @fcmgttest(<4 x float> %A, <4 x float> %B) { 73 call <4 x float> @llvm.spu.si.fcmgt(<4 x float> %A, <4 x float> %B) 74 %Y = bitcast <4 x float> %1 to <4 x float> 75 ret <4 x float> %Y 76 } 77 78 define <4 x float> @fmatest(<4 x float> %A, <4 x float> %B, <4 x float> %C) { 79 call <4 x float> @llvm.spu.si.fma(<4 x float> %A, <4 x float> %B, <4 x float> %C) 80 %Y = bitcast <4 x float> %1 to <4 x float> 81 ret <4 x float> %Y 82 } 83 84 define <4 x float> @fnmstest(<4 x float> %A, <4 x float> %B, <4 x float> %C) { 85 call <4 x float> @llvm.spu.si.fnms(<4 x float> %A, <4 x float> %B, <4 x float> %C) 86 %Y = bitcast <4 x float> %1 to <4 x float> 87 ret <4 x float> %Y 88 } 89 90 define <4 x float> @fmstest(<4 x float> %A, <4 x float> %B, <4 x float> %C) { 91 call <4 x float> @llvm.spu.si.fms(<4 x float> %A, <4 x float> %B, <4 x float> %C) 92 %Y = bitcast <4 x float> %1 to <4 x float> 93 ret <4 x float> %Y 94 } 95
