1 ; RUN: llc < %s -march=cellspu > %t1.s 2 ; RUN: grep {shlh } %t1.s | count 10 3 ; RUN: grep {shlhi } %t1.s | count 3 4 ; RUN: grep {shl } %t1.s | count 11 5 ; RUN: grep {shli } %t1.s | count 3 6 ; RUN: grep {xshw } %t1.s | count 5 7 ; RUN: grep {and } %t1.s | count 14 8 ; RUN: grep {andi } %t1.s | count 2 9 ; RUN: grep {rotmi } %t1.s | count 2 10 ; RUN: grep {rotqmbyi } %t1.s | count 1 11 ; RUN: grep {rotqmbii } %t1.s | count 2 12 ; RUN: grep {rotqmby } %t1.s | count 1 13 ; RUN: grep {rotqmbi } %t1.s | count 2 14 ; RUN: grep {rotqbyi } %t1.s | count 1 15 ; RUN: grep {rotqbii } %t1.s | count 2 16 ; RUN: grep {rotqbybi } %t1.s | count 1 17 ; RUN: grep {sfi } %t1.s | count 6 18 ; RUN: cat %t1.s | FileCheck %s 19 20 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" 21 target triple = "spu" 22 23 ; Shift left i16 via register, note that the second operand to shl is promoted 24 ; to a 32-bit type: 25 26 define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) { 27 %A = shl i16 %arg1, %arg2 28 ret i16 %A 29 } 30 31 define i16 @shlh_i16_2(i16 %arg1, i16 %arg2) { 32 %A = shl i16 %arg2, %arg1 33 ret i16 %A 34 } 35 36 define signext i16 @shlh_i16_3(i16 signext %arg1, i16 signext %arg2) { 37 %A = shl i16 %arg1, %arg2 38 ret i16 %A 39 } 40 41 define signext i16 @shlh_i16_4(i16 signext %arg1, i16 signext %arg2) { 42 %A = shl i16 %arg2, %arg1 43 ret i16 %A 44 } 45 46 define zeroext i16 @shlh_i16_5(i16 zeroext %arg1, i16 zeroext %arg2) { 47 %A = shl i16 %arg1, %arg2 48 ret i16 %A 49 } 50 51 define zeroext i16 @shlh_i16_6(i16 zeroext %arg1, i16 zeroext %arg2) { 52 %A = shl i16 %arg2, %arg1 53 ret i16 %A 54 } 55 56 ; Shift left i16 with immediate: 57 define i16 @shlhi_i16_1(i16 %arg1) { 58 %A = shl i16 %arg1, 12 59 ret i16 %A 60 } 61 62 ; Should not generate anything other than the return, arg1 << 0 = arg1 63 define i16 @shlhi_i16_2(i16 %arg1) { 64 %A = shl i16 %arg1, 0 65 ret i16 %A 66 } 67 68 define i16 @shlhi_i16_3(i16 %arg1) { 69 %A = shl i16 16383, %arg1 70 ret i16 %A 71 } 72 73 ; Should generate 0, 0 << arg1 = 0 74 define i16 @shlhi_i16_4(i16 %arg1) { 75 %A = shl i16 0, %arg1 76 ret i16 %A 77 } 78 79 define signext i16 @shlhi_i16_5(i16 signext %arg1) { 80 %A = shl i16 %arg1, 12 81 ret i16 %A 82 } 83 84 ; Should not generate anything other than the return, arg1 << 0 = arg1 85 define signext i16 @shlhi_i16_6(i16 signext %arg1) { 86 %A = shl i16 %arg1, 0 87 ret i16 %A 88 } 89 90 define signext i16 @shlhi_i16_7(i16 signext %arg1) { 91 %A = shl i16 16383, %arg1 92 ret i16 %A 93 } 94 95 ; Should generate 0, 0 << arg1 = 0 96 define signext i16 @shlhi_i16_8(i16 signext %arg1) { 97 %A = shl i16 0, %arg1 98 ret i16 %A 99 } 100 101 define zeroext i16 @shlhi_i16_9(i16 zeroext %arg1) { 102 %A = shl i16 %arg1, 12 103 ret i16 %A 104 } 105 106 ; Should not generate anything other than the return, arg1 << 0 = arg1 107 define zeroext i16 @shlhi_i16_10(i16 zeroext %arg1) { 108 %A = shl i16 %arg1, 0 109 ret i16 %A 110 } 111 112 define zeroext i16 @shlhi_i16_11(i16 zeroext %arg1) { 113 %A = shl i16 16383, %arg1 114 ret i16 %A 115 } 116 117 ; Should generate 0, 0 << arg1 = 0 118 define zeroext i16 @shlhi_i16_12(i16 zeroext %arg1) { 119 %A = shl i16 0, %arg1 120 ret i16 %A 121 } 122 123 ; Shift left i32 via register, note that the second operand to shl is promoted 124 ; to a 32-bit type: 125 126 define i32 @shl_i32_1(i32 %arg1, i32 %arg2) { 127 %A = shl i32 %arg1, %arg2 128 ret i32 %A 129 } 130 131 define i32 @shl_i32_2(i32 %arg1, i32 %arg2) { 132 %A = shl i32 %arg2, %arg1 133 ret i32 %A 134 } 135 136 define signext i32 @shl_i32_3(i32 signext %arg1, i32 signext %arg2) { 137 %A = shl i32 %arg1, %arg2 138 ret i32 %A 139 } 140 141 define signext i32 @shl_i32_4(i32 signext %arg1, i32 signext %arg2) { 142 %A = shl i32 %arg2, %arg1 143 ret i32 %A 144 } 145 146 define zeroext i32 @shl_i32_5(i32 zeroext %arg1, i32 zeroext %arg2) { 147 %A = shl i32 %arg1, %arg2 148 ret i32 %A 149 } 150 151 define zeroext i32 @shl_i32_6(i32 zeroext %arg1, i32 zeroext %arg2) { 152 %A = shl i32 %arg2, %arg1 153 ret i32 %A 154 } 155 156 ; Shift left i32 with immediate: 157 define i32 @shli_i32_1(i32 %arg1) { 158 %A = shl i32 %arg1, 12 159 ret i32 %A 160 } 161 162 ; Should not generate anything other than the return, arg1 << 0 = arg1 163 define i32 @shli_i32_2(i32 %arg1) { 164 %A = shl i32 %arg1, 0 165 ret i32 %A 166 } 167 168 define i32 @shli_i32_3(i32 %arg1) { 169 %A = shl i32 16383, %arg1 170 ret i32 %A 171 } 172 173 ; Should generate 0, 0 << arg1 = 0 174 define i32 @shli_i32_4(i32 %arg1) { 175 %A = shl i32 0, %arg1 176 ret i32 %A 177 } 178 179 define signext i32 @shli_i32_5(i32 signext %arg1) { 180 %A = shl i32 %arg1, 12 181 ret i32 %A 182 } 183 184 ; Should not generate anything other than the return, arg1 << 0 = arg1 185 define signext i32 @shli_i32_6(i32 signext %arg1) { 186 %A = shl i32 %arg1, 0 187 ret i32 %A 188 } 189 190 define signext i32 @shli_i32_7(i32 signext %arg1) { 191 %A = shl i32 16383, %arg1 192 ret i32 %A 193 } 194 195 ; Should generate 0, 0 << arg1 = 0 196 define signext i32 @shli_i32_8(i32 signext %arg1) { 197 %A = shl i32 0, %arg1 198 ret i32 %A 199 } 200 201 define zeroext i32 @shli_i32_9(i32 zeroext %arg1) { 202 %A = shl i32 %arg1, 12 203 ret i32 %A 204 } 205 206 ; Should not generate anything other than the return, arg1 << 0 = arg1 207 define zeroext i32 @shli_i32_10(i32 zeroext %arg1) { 208 %A = shl i32 %arg1, 0 209 ret i32 %A 210 } 211 212 define zeroext i32 @shli_i32_11(i32 zeroext %arg1) { 213 %A = shl i32 16383, %arg1 214 ret i32 %A 215 } 216 217 ; Should generate 0, 0 << arg1 = 0 218 define zeroext i32 @shli_i32_12(i32 zeroext %arg1) { 219 %A = shl i32 0, %arg1 220 ret i32 %A 221 } 222 223 ;; i64 shift left 224 225 define i64 @shl_i64_1(i64 %arg1) { 226 %A = shl i64 %arg1, 9 227 ret i64 %A 228 } 229 230 define i64 @shl_i64_2(i64 %arg1) { 231 %A = shl i64 %arg1, 3 232 ret i64 %A 233 } 234 235 define i64 @shl_i64_3(i64 %arg1, i32 %shift) { 236 %1 = zext i32 %shift to i64 237 %2 = shl i64 %arg1, %1 238 ret i64 %2 239 } 240 241 ;; i64 shift right logical (shift 0s from the right) 242 243 define i64 @lshr_i64_1(i64 %arg1) { 244 %1 = lshr i64 %arg1, 9 245 ret i64 %1 246 } 247 248 define i64 @lshr_i64_2(i64 %arg1) { 249 %1 = lshr i64 %arg1, 3 250 ret i64 %1 251 } 252 253 define i64 @lshr_i64_3(i64 %arg1, i32 %shift) { 254 %1 = zext i32 %shift to i64 255 %2 = lshr i64 %arg1, %1 256 ret i64 %2 257 } 258 259 ;; i64 shift right arithmetic (shift 1s from the right) 260 261 define i64 @ashr_i64_1(i64 %arg) { 262 %1 = ashr i64 %arg, 9 263 ret i64 %1 264 } 265 266 define i64 @ashr_i64_2(i64 %arg) { 267 %1 = ashr i64 %arg, 3 268 ret i64 %1 269 } 270 271 define i64 @ashr_i64_3(i64 %arg1, i32 %shift) { 272 %1 = zext i32 %shift to i64 273 %2 = ashr i64 %arg1, %1 274 ret i64 %2 275 } 276 277 define i32 @hi32_i64(i64 %arg) { 278 %1 = lshr i64 %arg, 32 279 %2 = trunc i64 %1 to i32 280 ret i32 %2 281 } 282 283 ; some random tests 284 define i128 @test_lshr_i128( i128 %val ) { 285 ;CHECK: test_lshr_i128 286 ;CHECK: sfi 287 ;CHECK: rotqmbi 288 ;CHECK: rotqmbybi 289 ;CHECK: bi $lr 290 %rv = lshr i128 %val, 64 291 ret i128 %rv 292 } 293 294 ;Vector shifts 295 define <2 x i32> @shl_v2i32(<2 x i32> %val, <2 x i32> %sh) { 296 ;CHECK: shl 297 ;CHECK: bi $lr 298 %rv = shl <2 x i32> %val, %sh 299 ret <2 x i32> %rv 300 } 301 302 define <4 x i32> @shl_v4i32(<4 x i32> %val, <4 x i32> %sh) { 303 ;CHECK: shl 304 ;CHECK: bi $lr 305 %rv = shl <4 x i32> %val, %sh 306 ret <4 x i32> %rv 307 } 308 309 define <8 x i16> @shl_v8i16(<8 x i16> %val, <8 x i16> %sh) { 310 ;CHECK: shlh 311 ;CHECK: bi $lr 312 %rv = shl <8 x i16> %val, %sh 313 ret <8 x i16> %rv 314 } 315 316 define <4 x i32> @lshr_v4i32(<4 x i32> %val, <4 x i32> %sh) { 317 ;CHECK: rotm 318 ;CHECK: bi $lr 319 %rv = lshr <4 x i32> %val, %sh 320 ret <4 x i32> %rv 321 } 322 323 define <8 x i16> @lshr_v8i16(<8 x i16> %val, <8 x i16> %sh) { 324 ;CHECK: sfhi 325 ;CHECK: rothm 326 ;CHECK: bi $lr 327 %rv = lshr <8 x i16> %val, %sh 328 ret <8 x i16> %rv 329 } 330 331 define <4 x i32> @ashr_v4i32(<4 x i32> %val, <4 x i32> %sh) { 332 ;CHECK: rotma 333 ;CHECK: bi $lr 334 %rv = ashr <4 x i32> %val, %sh 335 ret <4 x i32> %rv 336 } 337 338 define <8 x i16> @ashr_v8i16(<8 x i16> %val, <8 x i16> %sh) { 339 ;CHECK: sfhi 340 ;CHECK: rotmah 341 ;CHECK: bi $lr 342 %rv = ashr <8 x i16> %val, %sh 343 ret <8 x i16> %rv 344 } 345
