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      1 ; RUN: llc -O1  --march=cellspu < %s | FileCheck %s
      2 
      3 define <4 x float> @shuffle(<4 x float> %param1, <4 x float> %param2) {
      4   ; CHECK: cwd {{\$.}}, 0($sp)
      5   ; CHECK: shufb {{\$., \$4, \$3, \$.}}
      6   %val= shufflevector <4 x float> %param1, <4 x float> %param2, <4 x i32> <i32 4,i32 1,i32 2,i32 3>
      7   ret <4 x float> %val
      8 }
      9  
     10 define <4 x float> @splat(float %param1) {
     11   ; CHECK: lqa
     12   ; CHECK: shufb $3
     13   ; CHECK: bi
     14   %vec = insertelement <1 x float> undef, float %param1, i32 0
     15   %val= shufflevector <1 x float> %vec, <1 x float> undef, <4 x i32> <i32 0,i32 0,i32 0,i32 0>
     16   ret <4 x float> %val  
     17 }
     18 
     19 define void @test_insert( <2 x float>* %ptr, float %val1, float %val2 ) {
     20   %sl2_17_tmp1 = insertelement <2 x float> zeroinitializer, float %val1, i32 0
     21 ;CHECK:	lqa	$6,
     22 ;CHECK:	shufb	$4, $4, $5, $6
     23   %sl2_17 = insertelement <2 x float> %sl2_17_tmp1, float %val2, i32 1
     24 
     25 ;CHECK: cdd	$5, 0($3)
     26 ;CHECK: lqd	$6, 0($3)
     27 ;CHECK: shufb	$4, $4, $6, $5
     28 ;CHECK: stqd	$4, 0($3)
     29 ;CHECK:	bi	$lr
     30   store <2 x float> %sl2_17, <2 x float>* %ptr
     31   ret void 
     32 }
     33 
     34 define <4 x float>  @test_insert_1(<4 x float> %vparam, float %eltparam) {
     35 ;CHECK: cwd     $5, 4($sp)
     36 ;CHECK: shufb   $3, $4, $3, $5
     37 ;CHECK: bi      $lr
     38   %rv = insertelement <4 x float> %vparam, float %eltparam, i32 1
     39   ret <4 x float> %rv
     40 }
     41 
     42 define <2 x i32> @test_v2i32(<4 x i32>%vec)
     43 {
     44 ;CHECK: rotqbyi $3, $3, 4
     45 ;CHECK: bi $lr
     46   %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, <2 x i32><i32 1,i32 2>
     47   ret <2 x i32> %rv
     48 }
     49 
     50 define <4 x i32> @test_v4i32_rot8(<4 x i32>%vec)
     51 {
     52 ;CHECK: rotqbyi $3, $3, 8
     53 ;CHECK: bi $lr
     54   %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, 
     55         <4 x i32> <i32 2,i32 3,i32 0, i32 1>
     56   ret <4 x i32> %rv
     57 }
     58 
     59 define <4 x i32> @test_v4i32_rot4(<4 x i32>%vec)
     60 {
     61 ;CHECK: rotqbyi $3, $3, 4
     62 ;CHECK: bi $lr
     63   %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, 
     64         <4 x i32> <i32 1,i32 2,i32 3, i32 0>
     65   ret <4 x i32> %rv
     66 }
     67 
     68