Home | History | Annotate | Download | only in CellSPU 
      1 ; RUN: llc < %s -march=cellspu > %t1.s
      2 ; RUN: llc < %s -march=cellspu -mattr=large_mem > %t2.s
      3 ; RUN: grep -w il  %t1.s | count 3
      4 ; RUN: grep ilhu   %t1.s | count 8
      5 ; RUN: grep -w ilh %t1.s | count 5
      6 ; RUN: grep iohl   %t1.s | count 7
      7 ; RUN: grep lqa    %t1.s | count 6
      8 ; RUN: grep 24672  %t1.s | count 2
      9 ; RUN: grep 16429  %t1.s | count 1
     10 ; RUN: grep 63572  %t1.s | count 1
     11 ; RUN: grep  4660  %t1.s | count 1
     12 ; RUN: grep 22136  %t1.s | count 1
     13 ; RUN: grep 43981  %t1.s | count 1
     14 ; RUN: grep 61202  %t1.s | count 1
     15 ; RUN: grep 16393  %t1.s | count 1
     16 ; RUN: grep  8699  %t1.s | count 1
     17 ; RUN: grep 21572  %t1.s | count 1
     18 ; RUN: grep 11544  %t1.s | count 1
     19 ; RUN: grep 1311768467750121234 %t1.s | count 1
     20 ; RUN: grep lqd    %t2.s | count 6
     21 
     22 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
     23 target triple = "spu-unknown-elf"
     24 
     25 ; Vector constant load tests:
     26 
     27 ; IL <reg>, 2
     28 define <4 x i32> @v4i32_constvec() {
     29         ret <4 x i32> < i32 2, i32 2, i32 2, i32 2 >
     30 }
     31 
     32 ; Spill to constant pool
     33 define <4 x i32> @v4i32_constpool() {
     34         ret <4 x i32> < i32 2, i32 1, i32 1, i32 2 >
     35 }
     36 
     37 ; Max negative range for IL
     38 define <4 x i32> @v4i32_constvec_2() {
     39         ret <4 x i32> < i32 -32768, i32 -32768, i32 -32768, i32 -32768 >
     40 }
     41 
     42 ; ILHU <reg>, 73 (0x49)
     43 ; 4784128 = 0x490000
     44 define <4 x i32> @v4i32_constvec_3() {
     45         ret <4 x i32> < i32 4784128, i32 4784128,
     46                         i32 4784128, i32 4784128 >
     47 }
     48 
     49 ; ILHU <reg>, 61 (0x3d)
     50 ; IOHL <reg>, 15395 (0x3c23)
     51 define <4 x i32> @v4i32_constvec_4() {
     52         ret <4 x i32> < i32 4013091, i32 4013091,
     53                         i32 4013091, i32 4013091 >
     54 }
     55 
     56 ; ILHU <reg>, 0x5050 (20560)
     57 ; IOHL <reg>, 0x5050 (20560)
     58 ; Tests for whether we expand the size of the bit pattern properly, because
     59 ; this could be interpreted as an i8 pattern (0x50)
     60 define <4 x i32> @v4i32_constvec_5() {
     61         ret <4 x i32> < i32 1347440720, i32 1347440720,
     62                         i32 1347440720, i32 1347440720 >
     63 }
     64 
     65 ; ILH
     66 define <8 x i16> @v8i16_constvec_1() {
     67         ret <8 x i16> < i16 32767, i16 32767, i16 32767, i16 32767,
     68                         i16 32767, i16 32767, i16 32767, i16 32767 >
     69 }
     70 
     71 ; ILH
     72 define <8 x i16> @v8i16_constvec_2() {
     73         ret <8 x i16> < i16 511, i16 511, i16 511, i16 511, i16 511,
     74                         i16 511, i16 511, i16 511 >
     75 }
     76 
     77 ; ILH
     78 define <8 x i16> @v8i16_constvec_3() {
     79         ret <8 x i16> < i16 -512, i16 -512, i16 -512, i16 -512, i16 -512,
     80                         i16 -512, i16 -512, i16 -512 >
     81 }
     82 
     83 ; ILH <reg>, 24672 (0x6060)
     84 ; Tests whether we expand the size of the bit pattern properly, because
     85 ; this could be interpreted as an i8 pattern (0x60)
     86 define <8 x i16> @v8i16_constvec_4() {
     87         ret <8 x i16> < i16 24672, i16 24672, i16 24672, i16 24672, i16 24672,
     88                         i16 24672, i16 24672, i16 24672 >
     89 }
     90 
     91 ; ILH <reg>, 24672 (0x6060)
     92 ; Tests whether we expand the size of the bit pattern properly, because
     93 ; this is an i8 pattern but has to be expanded out to i16 to load it
     94 ; properly into the vector register.
     95 define <16 x i8> @v16i8_constvec_1() {
     96         ret <16 x i8> < i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96,
     97                         i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96 >
     98 }
     99 
    100 define <4 x float> @v4f32_constvec_1() {
    101 entry:
    102         ret <4 x float> < float 0x4005BF0A80000000,
    103                           float 0x4005BF0A80000000,
    104                           float 0x4005BF0A80000000,
    105                           float 0x4005BF0A80000000 >
    106 }
    107 
    108 define <4 x float> @v4f32_constvec_2() {
    109 entry:
    110         ret <4 x float> < float 0.000000e+00,
    111                           float 0.000000e+00,
    112                           float 0.000000e+00,
    113                           float 0.000000e+00 >
    114 }
    115 
    116 
    117 define <4 x float> @v4f32_constvec_3() {
    118 entry:
    119         ret <4 x float> < float 0x4005BF0A80000000,
    120                           float 0x3810000000000000,
    121                           float 0x47EFFFFFE0000000,
    122                           float 0x400921FB60000000 >
    123 }
    124 
    125 ;  1311768467750121234 => 0x 12345678 abcdef12
    126 ;  HI32_hi:  4660
    127 ;  HI32_lo: 22136
    128 ;  LO32_hi: 43981
    129 ;  LO32_lo: 61202
    130 define <2 x i64> @i64_constvec_1() {
    131 entry:
    132         ret <2 x i64> < i64 1311768467750121234,
    133                         i64 1311768467750121234 >
    134 }
    135 
    136 define <2 x i64> @i64_constvec_2() {
    137 entry:
    138         ret <2 x i64> < i64 1, i64 1311768467750121234 >
    139 }
    140 
    141 define <2 x double> @f64_constvec_1() {
    142 entry:
    143  ret <2 x double> < double 0x400921fb54442d18,
    144                     double 0xbff6a09e667f3bcd >
    145 }
    146 
    147 ; 0x400921fb 54442d18 ->
    148 ;   (ILHU 0x4009 [16393]/IOHL 0x21fb [ 8699])
    149 ;   (ILHU 0x5444 [21572]/IOHL 0x2d18 [11544])
    150 define <2 x double> @f64_constvec_2() {
    151 entry:
    152  ret <2 x double> < double 0x400921fb54442d18,
    153                     double 0x400921fb54442d18 >
    154 }
    155