1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/ADT/SmallSet.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <assert.h> 26 #include <string.h> 27 28 // Include the platform-specific parts of this class. 29 #ifdef LLVM_ON_UNIX 30 #include "Unix/Host.inc" 31 #endif 32 #ifdef LLVM_ON_WIN32 33 #include "Windows/Host.inc" 34 #endif 35 #ifdef _MSC_VER 36 #include <intrin.h> 37 #endif 38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 39 #include <mach/host_info.h> 40 #include <mach/mach.h> 41 #include <mach/mach_host.h> 42 #include <mach/machine.h> 43 #endif 44 45 #define DEBUG_TYPE "host-detection" 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Implementations of the CPU detection routines 50 // 51 //===----------------------------------------------------------------------===// 52 53 using namespace llvm; 54 55 #if defined(__linux__) 56 static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) { 57 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting 58 // memory buffer because the 'file' has 0 size (it can be read from only 59 // as a stream). 60 61 int FD; 62 std::error_code EC = sys::fs::openFileForRead("/proc/cpuinfo", FD); 63 if (EC) { 64 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << EC.message() << "\n"); 65 return -1; 66 } 67 int Ret = read(FD, Buf, Size); 68 int CloseStatus = close(FD); 69 if (CloseStatus) 70 return -1; 71 return Ret; 72 } 73 #endif 74 75 #if defined(__i386__) || defined(_M_IX86) || \ 76 defined(__x86_64__) || defined(_M_X64) 77 78 enum VendorSignatures { 79 SIG_INTEL = 0x756e6547 /* Genu */, 80 SIG_AMD = 0x68747541 /* Auth */ 81 }; 82 83 enum ProcessorVendors { 84 VENDOR_INTEL = 1, 85 VENDOR_AMD, 86 VENDOR_OTHER, 87 VENDOR_MAX 88 }; 89 90 enum ProcessorTypes { 91 INTEL_ATOM = 1, 92 INTEL_CORE2, 93 INTEL_COREI7, 94 AMDFAM10H, 95 AMDFAM15H, 96 INTEL_i386, 97 INTEL_i486, 98 INTEL_PENTIUM, 99 INTEL_PENTIUM_PRO, 100 INTEL_PENTIUM_II, 101 INTEL_PENTIUM_III, 102 INTEL_PENTIUM_IV, 103 INTEL_PENTIUM_M, 104 INTEL_CORE_DUO, 105 INTEL_XEONPHI, 106 INTEL_X86_64, 107 INTEL_NOCONA, 108 INTEL_PRESCOTT, 109 AMD_i486, 110 AMDPENTIUM, 111 AMDATHLON, 112 AMDFAM14H, 113 AMDFAM16H, 114 CPU_TYPE_MAX 115 }; 116 117 enum ProcessorSubtypes { 118 INTEL_COREI7_NEHALEM = 1, 119 INTEL_COREI7_WESTMERE, 120 INTEL_COREI7_SANDYBRIDGE, 121 AMDFAM10H_BARCELONA, 122 AMDFAM10H_SHANGHAI, 123 AMDFAM10H_ISTANBUL, 124 AMDFAM15H_BDVER1, 125 AMDFAM15H_BDVER2, 126 INTEL_PENTIUM_MMX, 127 INTEL_CORE2_65, 128 INTEL_CORE2_45, 129 INTEL_COREI7_IVYBRIDGE, 130 INTEL_COREI7_HASWELL, 131 INTEL_COREI7_BROADWELL, 132 INTEL_COREI7_SKYLAKE, 133 INTEL_COREI7_SKYLAKE_AVX512, 134 INTEL_ATOM_BONNELL, 135 INTEL_ATOM_SILVERMONT, 136 INTEL_KNIGHTS_LANDING, 137 AMDPENTIUM_K6, 138 AMDPENTIUM_K62, 139 AMDPENTIUM_K63, 140 AMDPENTIUM_GEODE, 141 AMDATHLON_TBIRD, 142 AMDATHLON_MP, 143 AMDATHLON_XP, 144 AMDATHLON_K8SSE3, 145 AMDATHLON_OPTERON, 146 AMDATHLON_FX, 147 AMDATHLON_64, 148 AMD_BTVER1, 149 AMD_BTVER2, 150 AMDFAM15H_BDVER3, 151 AMDFAM15H_BDVER4, 152 CPU_SUBTYPE_MAX 153 }; 154 155 enum ProcessorFeatures { 156 FEATURE_CMOV = 0, 157 FEATURE_MMX, 158 FEATURE_POPCNT, 159 FEATURE_SSE, 160 FEATURE_SSE2, 161 FEATURE_SSE3, 162 FEATURE_SSSE3, 163 FEATURE_SSE4_1, 164 FEATURE_SSE4_2, 165 FEATURE_AVX, 166 FEATURE_AVX2, 167 FEATURE_AVX512, 168 FEATURE_AVX512SAVE, 169 FEATURE_MOVBE, 170 FEATURE_ADX, 171 FEATURE_EM64T 172 }; 173 174 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 175 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 176 // support. Consequently, for i386, the presence of CPUID is checked first 177 // via the corresponding eflags bit. 178 // Removal of cpuid.h header motivated by PR30384 179 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 180 // or test-suite, but are used in external projects e.g. libstdcxx 181 static bool isCpuIdSupported() { 182 #if defined(__GNUC__) || defined(__clang__) 183 #if defined(__i386__) 184 int __cpuid_supported; 185 __asm__(" pushfl\n" 186 " popl %%eax\n" 187 " movl %%eax,%%ecx\n" 188 " xorl $0x00200000,%%eax\n" 189 " pushl %%eax\n" 190 " popfl\n" 191 " pushfl\n" 192 " popl %%eax\n" 193 " movl $0,%0\n" 194 " cmpl %%eax,%%ecx\n" 195 " je 1f\n" 196 " movl $1,%0\n" 197 "1:" 198 : "=r"(__cpuid_supported) 199 : 200 : "eax", "ecx"); 201 if (!__cpuid_supported) 202 return false; 203 #endif 204 return true; 205 #endif 206 return true; 207 } 208 209 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 210 /// the specified arguments. If we can't run cpuid on the host, return true. 211 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 212 unsigned *rECX, unsigned *rEDX) { 213 #if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER) 214 #if defined(__GNUC__) || defined(__clang__) 215 #if defined(__x86_64__) 216 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 217 // FIXME: should we save this for Clang? 218 __asm__("movq\t%%rbx, %%rsi\n\t" 219 "cpuid\n\t" 220 "xchgq\t%%rbx, %%rsi\n\t" 221 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 222 : "a"(value)); 223 #elif defined(__i386__) 224 __asm__("movl\t%%ebx, %%esi\n\t" 225 "cpuid\n\t" 226 "xchgl\t%%ebx, %%esi\n\t" 227 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 228 : "a"(value)); 229 #else 230 assert(0 && "This method is defined only for x86."); 231 #endif 232 #elif defined(_MSC_VER) 233 // The MSVC intrinsic is portable across x86 and x64. 234 int registers[4]; 235 __cpuid(registers, value); 236 *rEAX = registers[0]; 237 *rEBX = registers[1]; 238 *rECX = registers[2]; 239 *rEDX = registers[3]; 240 #endif 241 return false; 242 #else 243 return true; 244 #endif 245 } 246 247 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 248 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 249 /// return true. 250 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 251 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 252 unsigned *rEDX) { 253 #if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER) 254 #if defined(__x86_64__) || defined(_M_X64) 255 #if defined(__GNUC__) || defined(__clang__) 256 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 257 // FIXME: should we save this for Clang? 258 __asm__("movq\t%%rbx, %%rsi\n\t" 259 "cpuid\n\t" 260 "xchgq\t%%rbx, %%rsi\n\t" 261 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 262 : "a"(value), "c"(subleaf)); 263 #elif defined(_MSC_VER) 264 int registers[4]; 265 __cpuidex(registers, value, subleaf); 266 *rEAX = registers[0]; 267 *rEBX = registers[1]; 268 *rECX = registers[2]; 269 *rEDX = registers[3]; 270 #endif 271 #elif defined(__i386__) || defined(_M_IX86) 272 #if defined(__GNUC__) || defined(__clang__) 273 __asm__("movl\t%%ebx, %%esi\n\t" 274 "cpuid\n\t" 275 "xchgl\t%%ebx, %%esi\n\t" 276 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 277 : "a"(value), "c"(subleaf)); 278 #elif defined(_MSC_VER) 279 __asm { 280 mov eax,value 281 mov ecx,subleaf 282 cpuid 283 mov esi,rEAX 284 mov dword ptr [esi],eax 285 mov esi,rEBX 286 mov dword ptr [esi],ebx 287 mov esi,rECX 288 mov dword ptr [esi],ecx 289 mov esi,rEDX 290 mov dword ptr [esi],edx 291 } 292 #endif 293 #else 294 assert(0 && "This method is defined only for x86."); 295 #endif 296 return false; 297 #else 298 return true; 299 #endif 300 } 301 302 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 303 #if defined(__GNUC__) || defined(__clang__) 304 // Check xgetbv; this uses a .byte sequence instead of the instruction 305 // directly because older assemblers do not include support for xgetbv and 306 // there is no easy way to conditionally compile based on the assembler used. 307 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 308 return false; 309 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 310 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 311 *rEAX = Result; 312 *rEDX = Result >> 32; 313 return false; 314 #else 315 return true; 316 #endif 317 } 318 319 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 320 unsigned *Model) { 321 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 322 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 323 if (*Family == 6 || *Family == 0xf) { 324 if (*Family == 0xf) 325 // Examine extended family ID if family ID is F. 326 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 327 // Examine extended model ID if family ID is 6 or F. 328 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 329 } 330 } 331 332 static void 333 getIntelProcessorTypeAndSubtype(unsigned int Family, unsigned int Model, 334 unsigned int Brand_id, unsigned int Features, 335 unsigned *Type, unsigned *Subtype) { 336 if (Brand_id != 0) 337 return; 338 switch (Family) { 339 case 3: 340 *Type = INTEL_i386; 341 break; 342 case 4: 343 switch (Model) { 344 case 0: // Intel486 DX processors 345 case 1: // Intel486 DX processors 346 case 2: // Intel486 SX processors 347 case 3: // Intel487 processors, IntelDX2 OverDrive processors, 348 // IntelDX2 processors 349 case 4: // Intel486 SL processor 350 case 5: // IntelSX2 processors 351 case 7: // Write-Back Enhanced IntelDX2 processors 352 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors 353 default: 354 *Type = INTEL_i486; 355 break; 356 } 357 break; 358 case 5: 359 switch (Model) { 360 case 1: // Pentium OverDrive processor for Pentium processor (60, 66), 361 // Pentium processors (60, 66) 362 case 2: // Pentium OverDrive processor for Pentium processor (75, 90, 363 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, 364 // 150, 166, 200) 365 case 3: // Pentium OverDrive processors for Intel486 processor-based 366 // systems 367 *Type = INTEL_PENTIUM; 368 break; 369 case 4: // Pentium OverDrive processor with MMX technology for Pentium 370 // processor (75, 90, 100, 120, 133), Pentium processor with 371 // MMX technology (166, 200) 372 *Type = INTEL_PENTIUM; 373 *Subtype = INTEL_PENTIUM_MMX; 374 break; 375 default: 376 *Type = INTEL_PENTIUM; 377 break; 378 } 379 break; 380 case 6: 381 switch (Model) { 382 case 0x01: // Pentium Pro processor 383 *Type = INTEL_PENTIUM_PRO; 384 break; 385 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 386 // model 03 387 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 388 // model 05, and Intel Celeron processor, model 05 389 case 0x06: // Celeron processor, model 06 390 *Type = INTEL_PENTIUM_II; 391 break; 392 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 393 // processor, model 07 394 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 395 // model 08, and Celeron processor, model 08 396 case 0x0a: // Pentium III Xeon processor, model 0Ah 397 case 0x0b: // Pentium III processor, model 0Bh 398 *Type = INTEL_PENTIUM_III; 399 break; 400 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 401 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 402 // 0Dh. All processors are manufactured using the 90 nm process. 403 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 404 // Integrated Processor with Intel QuickAssist Technology 405 *Type = INTEL_PENTIUM_M; 406 break; 407 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 408 // 0Eh. All processors are manufactured using the 65 nm process. 409 *Type = INTEL_CORE_DUO; 410 break; // yonah 411 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 412 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 413 // mobile processor, Intel Core 2 Extreme processor, Intel 414 // Pentium Dual-Core processor, Intel Xeon processor, model 415 // 0Fh. All processors are manufactured using the 65 nm process. 416 case 0x16: // Intel Celeron processor model 16h. All processors are 417 // manufactured using the 65 nm process 418 *Type = INTEL_CORE2; // "core2" 419 *Subtype = INTEL_CORE2_65; 420 break; 421 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 422 // 17h. All processors are manufactured using the 45 nm process. 423 // 424 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 425 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 426 // the 45 nm process. 427 *Type = INTEL_CORE2; // "penryn" 428 *Subtype = INTEL_CORE2_45; 429 break; 430 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 431 // processors are manufactured using the 45 nm process. 432 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 433 // As found in a Summer 2010 model iMac. 434 case 0x1f: 435 case 0x2e: // Nehalem EX 436 *Type = INTEL_COREI7; // "nehalem" 437 *Subtype = INTEL_COREI7_NEHALEM; 438 break; 439 case 0x25: // Intel Core i7, laptop version. 440 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 441 // processors are manufactured using the 32 nm process. 442 case 0x2f: // Westmere EX 443 *Type = INTEL_COREI7; // "westmere" 444 *Subtype = INTEL_COREI7_WESTMERE; 445 break; 446 case 0x2a: // Intel Core i7 processor. All processors are manufactured 447 // using the 32 nm process. 448 case 0x2d: 449 *Type = INTEL_COREI7; //"sandybridge" 450 *Subtype = INTEL_COREI7_SANDYBRIDGE; 451 break; 452 case 0x3a: 453 case 0x3e: // Ivy Bridge EP 454 *Type = INTEL_COREI7; // "ivybridge" 455 *Subtype = INTEL_COREI7_IVYBRIDGE; 456 break; 457 458 // Haswell: 459 case 0x3c: 460 case 0x3f: 461 case 0x45: 462 case 0x46: 463 *Type = INTEL_COREI7; // "haswell" 464 *Subtype = INTEL_COREI7_HASWELL; 465 break; 466 467 // Broadwell: 468 case 0x3d: 469 case 0x47: 470 case 0x4f: 471 case 0x56: 472 *Type = INTEL_COREI7; // "broadwell" 473 *Subtype = INTEL_COREI7_BROADWELL; 474 break; 475 476 // Skylake: 477 case 0x4e: 478 *Type = INTEL_COREI7; // "skylake-avx512" 479 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; 480 break; 481 case 0x5e: 482 *Type = INTEL_COREI7; // "skylake" 483 *Subtype = INTEL_COREI7_SKYLAKE; 484 break; 485 486 case 0x1c: // Most 45 nm Intel Atom processors 487 case 0x26: // 45 nm Atom Lincroft 488 case 0x27: // 32 nm Atom Medfield 489 case 0x35: // 32 nm Atom Midview 490 case 0x36: // 32 nm Atom Midview 491 *Type = INTEL_ATOM; 492 *Subtype = INTEL_ATOM_BONNELL; 493 break; // "bonnell" 494 495 // Atom Silvermont codes from the Intel software optimization guide. 496 case 0x37: 497 case 0x4a: 498 case 0x4d: 499 case 0x5a: 500 case 0x5d: 501 case 0x4c: // really airmont 502 *Type = INTEL_ATOM; 503 *Subtype = INTEL_ATOM_SILVERMONT; 504 break; // "silvermont" 505 506 case 0x57: 507 *Type = INTEL_XEONPHI; // knl 508 *Subtype = INTEL_KNIGHTS_LANDING; 509 break; 510 511 default: // Unknown family 6 CPU, try to guess. 512 if (Features & (1 << FEATURE_AVX512)) { 513 *Type = INTEL_XEONPHI; // knl 514 *Subtype = INTEL_KNIGHTS_LANDING; 515 break; 516 } 517 if (Features & (1 << FEATURE_ADX)) { 518 *Type = INTEL_COREI7; 519 *Subtype = INTEL_COREI7_BROADWELL; 520 break; 521 } 522 if (Features & (1 << FEATURE_AVX2)) { 523 *Type = INTEL_COREI7; 524 *Subtype = INTEL_COREI7_HASWELL; 525 break; 526 } 527 if (Features & (1 << FEATURE_AVX)) { 528 *Type = INTEL_COREI7; 529 *Subtype = INTEL_COREI7_SANDYBRIDGE; 530 break; 531 } 532 if (Features & (1 << FEATURE_SSE4_2)) { 533 if (Features & (1 << FEATURE_MOVBE)) { 534 *Type = INTEL_ATOM; 535 *Subtype = INTEL_ATOM_SILVERMONT; 536 } else { 537 *Type = INTEL_COREI7; 538 *Subtype = INTEL_COREI7_NEHALEM; 539 } 540 break; 541 } 542 if (Features & (1 << FEATURE_SSE4_1)) { 543 *Type = INTEL_CORE2; // "penryn" 544 *Subtype = INTEL_CORE2_45; 545 break; 546 } 547 if (Features & (1 << FEATURE_SSSE3)) { 548 if (Features & (1 << FEATURE_MOVBE)) { 549 *Type = INTEL_ATOM; 550 *Subtype = INTEL_ATOM_BONNELL; // "bonnell" 551 } else { 552 *Type = INTEL_CORE2; // "core2" 553 *Subtype = INTEL_CORE2_65; 554 } 555 break; 556 } 557 if (Features & (1 << FEATURE_EM64T)) { 558 *Type = INTEL_X86_64; 559 break; // x86-64 560 } 561 if (Features & (1 << FEATURE_SSE2)) { 562 *Type = INTEL_PENTIUM_M; 563 break; 564 } 565 if (Features & (1 << FEATURE_SSE)) { 566 *Type = INTEL_PENTIUM_III; 567 break; 568 } 569 if (Features & (1 << FEATURE_MMX)) { 570 *Type = INTEL_PENTIUM_II; 571 break; 572 } 573 *Type = INTEL_PENTIUM_PRO; 574 break; 575 } 576 break; 577 case 15: { 578 switch (Model) { 579 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are 580 // model 00h and manufactured using the 0.18 micron process. 581 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon 582 // processor MP, and Intel Celeron processor. All processors are 583 // model 01h and manufactured using the 0.18 micron process. 584 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, 585 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron 586 // processor, and Mobile Intel Celeron processor. All processors 587 // are model 02h and manufactured using the 0.13 micron process. 588 *Type = 589 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); 590 break; 591 592 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D 593 // processor. All processors are model 03h and manufactured using 594 // the 90 nm process. 595 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, 596 // Pentium D processor, Intel Xeon processor, Intel Xeon 597 // processor MP, Intel Celeron D processor. All processors are 598 // model 04h and manufactured using the 90 nm process. 599 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor 600 // Extreme Edition, Intel Xeon processor, Intel Xeon processor 601 // MP, Intel Celeron D processor. All processors are model 06h 602 // and manufactured using the 65 nm process. 603 *Type = 604 ((Features & (1 << FEATURE_EM64T)) ? INTEL_NOCONA : INTEL_PRESCOTT); 605 break; 606 607 default: 608 *Type = 609 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); 610 break; 611 } 612 break; 613 } 614 default: 615 break; /*"generic"*/ 616 } 617 } 618 619 static void getAMDProcessorTypeAndSubtype(unsigned int Family, 620 unsigned int Model, 621 unsigned int Features, 622 unsigned *Type, 623 unsigned *Subtype) { 624 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 625 // appears to be no way to generate the wide variety of AMD-specific targets 626 // from the information returned from CPUID. 627 switch (Family) { 628 case 4: 629 *Type = AMD_i486; 630 break; 631 case 5: 632 *Type = AMDPENTIUM; 633 switch (Model) { 634 case 6: 635 case 7: 636 *Subtype = AMDPENTIUM_K6; 637 break; // "k6" 638 case 8: 639 *Subtype = AMDPENTIUM_K62; 640 break; // "k6-2" 641 case 9: 642 case 13: 643 *Subtype = AMDPENTIUM_K63; 644 break; // "k6-3" 645 case 10: 646 *Subtype = AMDPENTIUM_GEODE; 647 break; // "geode" 648 } 649 break; 650 case 6: 651 *Type = AMDATHLON; 652 switch (Model) { 653 case 4: 654 *Subtype = AMDATHLON_TBIRD; 655 break; // "athlon-tbird" 656 case 6: 657 case 7: 658 case 8: 659 *Subtype = AMDATHLON_MP; 660 break; // "athlon-mp" 661 case 10: 662 *Subtype = AMDATHLON_XP; 663 break; // "athlon-xp" 664 } 665 break; 666 case 15: 667 *Type = AMDATHLON; 668 if (Features & (1 << FEATURE_SSE3)) { 669 *Subtype = AMDATHLON_K8SSE3; 670 break; // "k8-sse3" 671 } 672 switch (Model) { 673 case 1: 674 *Subtype = AMDATHLON_OPTERON; 675 break; // "opteron" 676 case 5: 677 *Subtype = AMDATHLON_FX; 678 break; // "athlon-fx"; also opteron 679 default: 680 *Subtype = AMDATHLON_64; 681 break; // "athlon64" 682 } 683 break; 684 case 16: 685 *Type = AMDFAM10H; // "amdfam10" 686 switch (Model) { 687 case 2: 688 *Subtype = AMDFAM10H_BARCELONA; 689 break; 690 case 4: 691 *Subtype = AMDFAM10H_SHANGHAI; 692 break; 693 case 8: 694 *Subtype = AMDFAM10H_ISTANBUL; 695 break; 696 } 697 break; 698 case 20: 699 *Type = AMDFAM14H; 700 *Subtype = AMD_BTVER1; 701 break; // "btver1"; 702 case 21: 703 *Type = AMDFAM15H; 704 if (!(Features & 705 (1 << FEATURE_AVX))) { // If no AVX support, provide a sane fallback. 706 *Subtype = AMD_BTVER1; 707 break; // "btver1" 708 } 709 if (Model >= 0x50 && Model <= 0x6f) { 710 *Subtype = AMDFAM15H_BDVER4; 711 break; // "bdver4"; 50h-6Fh: Excavator 712 } 713 if (Model >= 0x30 && Model <= 0x3f) { 714 *Subtype = AMDFAM15H_BDVER3; 715 break; // "bdver3"; 30h-3Fh: Steamroller 716 } 717 if (Model >= 0x10 && Model <= 0x1f) { 718 *Subtype = AMDFAM15H_BDVER2; 719 break; // "bdver2"; 10h-1Fh: Piledriver 720 } 721 if (Model <= 0x0f) { 722 *Subtype = AMDFAM15H_BDVER1; 723 break; // "bdver1"; 00h-0Fh: Bulldozer 724 } 725 break; 726 case 22: 727 *Type = AMDFAM16H; 728 if (!(Features & 729 (1 << FEATURE_AVX))) { // If no AVX support provide a sane fallback. 730 *Subtype = AMD_BTVER1; 731 break; // "btver1"; 732 } 733 *Subtype = AMD_BTVER2; 734 break; // "btver2" 735 default: 736 break; // "generic" 737 } 738 } 739 740 static unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX, 741 unsigned MaxLeaf) { 742 unsigned Features = 0; 743 unsigned int EAX, EBX; 744 Features |= (((EDX >> 23) & 1) << FEATURE_MMX); 745 Features |= (((EDX >> 25) & 1) << FEATURE_SSE); 746 Features |= (((EDX >> 26) & 1) << FEATURE_SSE2); 747 Features |= (((ECX >> 0) & 1) << FEATURE_SSE3); 748 Features |= (((ECX >> 9) & 1) << FEATURE_SSSE3); 749 Features |= (((ECX >> 19) & 1) << FEATURE_SSE4_1); 750 Features |= (((ECX >> 20) & 1) << FEATURE_SSE4_2); 751 Features |= (((ECX >> 22) & 1) << FEATURE_MOVBE); 752 753 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 754 // indicates that the AVX registers will be saved and restored on context 755 // switch, then we have full AVX support. 756 const unsigned AVXBits = (1 << 27) | (1 << 28); 757 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 758 ((EAX & 0x6) == 0x6); 759 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 760 bool HasLeaf7 = 761 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 762 bool HasADX = HasLeaf7 && ((EBX >> 19) & 1); 763 bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20); 764 bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1); 765 Features |= (HasAVX << FEATURE_AVX); 766 Features |= (HasAVX2 << FEATURE_AVX2); 767 Features |= (HasAVX512 << FEATURE_AVX512); 768 Features |= (HasAVX512Save << FEATURE_AVX512SAVE); 769 Features |= (HasADX << FEATURE_ADX); 770 771 getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 772 Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T); 773 return Features; 774 } 775 776 StringRef sys::getHostCPUName() { 777 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 778 unsigned MaxLeaf, Vendor; 779 780 #if defined(__GNUC__) || defined(__clang__) 781 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 782 // and simplify it to not invoke __cpuid (like cpu_model.c in 783 // compiler-rt/lib/builtins/cpu_model.c? 784 // Opting for the second option. 785 if(!isCpuIdSupported()) 786 return "generic"; 787 #endif 788 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX)) 789 return "generic"; 790 if (getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) 791 return "generic"; 792 793 unsigned Brand_id = EBX & 0xff; 794 unsigned Family = 0, Model = 0; 795 unsigned Features = 0; 796 detectX86FamilyModel(EAX, &Family, &Model); 797 Features = getAvailableFeatures(ECX, EDX, MaxLeaf); 798 799 unsigned Type; 800 unsigned Subtype; 801 802 if (Vendor == SIG_INTEL) { 803 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, &Type, 804 &Subtype); 805 switch (Type) { 806 case INTEL_i386: 807 return "i386"; 808 case INTEL_i486: 809 return "i486"; 810 case INTEL_PENTIUM: 811 if (Subtype == INTEL_PENTIUM_MMX) 812 return "pentium-mmx"; 813 return "pentium"; 814 case INTEL_PENTIUM_PRO: 815 return "pentiumpro"; 816 case INTEL_PENTIUM_II: 817 return "pentium2"; 818 case INTEL_PENTIUM_III: 819 return "pentium3"; 820 case INTEL_PENTIUM_IV: 821 return "pentium4"; 822 case INTEL_PENTIUM_M: 823 return "pentium-m"; 824 case INTEL_CORE_DUO: 825 return "yonah"; 826 case INTEL_CORE2: 827 switch (Subtype) { 828 case INTEL_CORE2_65: 829 return "core2"; 830 case INTEL_CORE2_45: 831 return "penryn"; 832 default: 833 return "core2"; 834 } 835 case INTEL_COREI7: 836 switch (Subtype) { 837 case INTEL_COREI7_NEHALEM: 838 return "nehalem"; 839 case INTEL_COREI7_WESTMERE: 840 return "westmere"; 841 case INTEL_COREI7_SANDYBRIDGE: 842 return "sandybridge"; 843 case INTEL_COREI7_IVYBRIDGE: 844 return "ivybridge"; 845 case INTEL_COREI7_HASWELL: 846 return "haswell"; 847 case INTEL_COREI7_BROADWELL: 848 return "broadwell"; 849 case INTEL_COREI7_SKYLAKE: 850 return "skylake"; 851 case INTEL_COREI7_SKYLAKE_AVX512: 852 return "skylake-avx512"; 853 default: 854 return "corei7"; 855 } 856 case INTEL_ATOM: 857 switch (Subtype) { 858 case INTEL_ATOM_BONNELL: 859 return "bonnell"; 860 case INTEL_ATOM_SILVERMONT: 861 return "silvermont"; 862 default: 863 return "atom"; 864 } 865 case INTEL_XEONPHI: 866 return "knl"; /*update for more variants added*/ 867 case INTEL_X86_64: 868 return "x86-64"; 869 case INTEL_NOCONA: 870 return "nocona"; 871 case INTEL_PRESCOTT: 872 return "prescott"; 873 default: 874 return "generic"; 875 } 876 } else if (Vendor == SIG_AMD) { 877 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 878 switch (Type) { 879 case AMD_i486: 880 return "i486"; 881 case AMDPENTIUM: 882 switch (Subtype) { 883 case AMDPENTIUM_K6: 884 return "k6"; 885 case AMDPENTIUM_K62: 886 return "k6-2"; 887 case AMDPENTIUM_K63: 888 return "k6-3"; 889 case AMDPENTIUM_GEODE: 890 return "geode"; 891 default: 892 return "pentium"; 893 } 894 case AMDATHLON: 895 switch (Subtype) { 896 case AMDATHLON_TBIRD: 897 return "athlon-tbird"; 898 case AMDATHLON_MP: 899 return "athlon-mp"; 900 case AMDATHLON_XP: 901 return "athlon-xp"; 902 case AMDATHLON_K8SSE3: 903 return "k8-sse3"; 904 case AMDATHLON_OPTERON: 905 return "opteron"; 906 case AMDATHLON_FX: 907 return "athlon-fx"; 908 case AMDATHLON_64: 909 return "athlon64"; 910 default: 911 return "athlon"; 912 } 913 case AMDFAM10H: 914 if(Subtype == AMDFAM10H_BARCELONA) 915 return "barcelona"; 916 return "amdfam10"; 917 case AMDFAM14H: 918 return "btver1"; 919 case AMDFAM15H: 920 switch (Subtype) { 921 case AMDFAM15H_BDVER1: 922 return "bdver1"; 923 case AMDFAM15H_BDVER2: 924 return "bdver2"; 925 case AMDFAM15H_BDVER3: 926 return "bdver3"; 927 case AMDFAM15H_BDVER4: 928 return "bdver4"; 929 case AMD_BTVER1: 930 return "btver1"; 931 default: 932 return "amdfam15"; 933 } 934 case AMDFAM16H: 935 switch (Subtype) { 936 case AMD_BTVER1: 937 return "btver1"; 938 case AMD_BTVER2: 939 return "btver2"; 940 default: 941 return "amdfam16"; 942 } 943 default: 944 return "generic"; 945 } 946 } 947 return "generic"; 948 } 949 950 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 951 StringRef sys::getHostCPUName() { 952 host_basic_info_data_t hostInfo; 953 mach_msg_type_number_t infoCount; 954 955 infoCount = HOST_BASIC_INFO_COUNT; 956 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, 957 &infoCount); 958 959 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 960 return "generic"; 961 962 switch (hostInfo.cpu_subtype) { 963 case CPU_SUBTYPE_POWERPC_601: 964 return "601"; 965 case CPU_SUBTYPE_POWERPC_602: 966 return "602"; 967 case CPU_SUBTYPE_POWERPC_603: 968 return "603"; 969 case CPU_SUBTYPE_POWERPC_603e: 970 return "603e"; 971 case CPU_SUBTYPE_POWERPC_603ev: 972 return "603ev"; 973 case CPU_SUBTYPE_POWERPC_604: 974 return "604"; 975 case CPU_SUBTYPE_POWERPC_604e: 976 return "604e"; 977 case CPU_SUBTYPE_POWERPC_620: 978 return "620"; 979 case CPU_SUBTYPE_POWERPC_750: 980 return "750"; 981 case CPU_SUBTYPE_POWERPC_7400: 982 return "7400"; 983 case CPU_SUBTYPE_POWERPC_7450: 984 return "7450"; 985 case CPU_SUBTYPE_POWERPC_970: 986 return "970"; 987 default:; 988 } 989 990 return "generic"; 991 } 992 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 993 StringRef sys::getHostCPUName() { 994 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 995 // and so we must use an operating-system interface to determine the current 996 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 997 const char *generic = "generic"; 998 999 // The cpu line is second (after the 'processor: 0' line), so if this 1000 // buffer is too small then something has changed (or is wrong). 1001 char buffer[1024]; 1002 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 1003 if (CPUInfoSize == -1) 1004 return generic; 1005 1006 const char *CPUInfoStart = buffer; 1007 const char *CPUInfoEnd = buffer + CPUInfoSize; 1008 1009 const char *CIP = CPUInfoStart; 1010 1011 const char *CPUStart = 0; 1012 size_t CPULen = 0; 1013 1014 // We need to find the first line which starts with cpu, spaces, and a colon. 1015 // After the colon, there may be some additional spaces and then the cpu type. 1016 while (CIP < CPUInfoEnd && CPUStart == 0) { 1017 if (CIP < CPUInfoEnd && *CIP == '\n') 1018 ++CIP; 1019 1020 if (CIP < CPUInfoEnd && *CIP == 'c') { 1021 ++CIP; 1022 if (CIP < CPUInfoEnd && *CIP == 'p') { 1023 ++CIP; 1024 if (CIP < CPUInfoEnd && *CIP == 'u') { 1025 ++CIP; 1026 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 1027 ++CIP; 1028 1029 if (CIP < CPUInfoEnd && *CIP == ':') { 1030 ++CIP; 1031 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 1032 ++CIP; 1033 1034 if (CIP < CPUInfoEnd) { 1035 CPUStart = CIP; 1036 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 1037 *CIP != ',' && *CIP != '\n')) 1038 ++CIP; 1039 CPULen = CIP - CPUStart; 1040 } 1041 } 1042 } 1043 } 1044 } 1045 1046 if (CPUStart == 0) 1047 while (CIP < CPUInfoEnd && *CIP != '\n') 1048 ++CIP; 1049 } 1050 1051 if (CPUStart == 0) 1052 return generic; 1053 1054 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 1055 .Case("604e", "604e") 1056 .Case("604", "604") 1057 .Case("7400", "7400") 1058 .Case("7410", "7400") 1059 .Case("7447", "7400") 1060 .Case("7455", "7450") 1061 .Case("G4", "g4") 1062 .Case("POWER4", "970") 1063 .Case("PPC970FX", "970") 1064 .Case("PPC970MP", "970") 1065 .Case("G5", "g5") 1066 .Case("POWER5", "g5") 1067 .Case("A2", "a2") 1068 .Case("POWER6", "pwr6") 1069 .Case("POWER7", "pwr7") 1070 .Case("POWER8", "pwr8") 1071 .Case("POWER8E", "pwr8") 1072 .Case("POWER9", "pwr9") 1073 .Default(generic); 1074 } 1075 #elif defined(__linux__) && defined(__arm__) 1076 StringRef sys::getHostCPUName() { 1077 // The cpuid register on arm is not accessible from user space. On Linux, 1078 // it is exposed through the /proc/cpuinfo file. 1079 1080 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line 1081 // in all cases. 1082 char buffer[1024]; 1083 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 1084 if (CPUInfoSize == -1) 1085 return "generic"; 1086 1087 StringRef Str(buffer, CPUInfoSize); 1088 1089 SmallVector<StringRef, 32> Lines; 1090 Str.split(Lines, "\n"); 1091 1092 // Look for the CPU implementer line. 1093 StringRef Implementer; 1094 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1095 if (Lines[I].startswith("CPU implementer")) 1096 Implementer = Lines[I].substr(15).ltrim("\t :"); 1097 1098 if (Implementer == "0x41") // ARM Ltd. 1099 // Look for the CPU part line. 1100 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1101 if (Lines[I].startswith("CPU part")) 1102 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 1103 // values correspond to the "Part number" in the CP15/c0 register. The 1104 // contents are specified in the various processor manuals. 1105 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 1106 .Case("0x926", "arm926ej-s") 1107 .Case("0xb02", "mpcore") 1108 .Case("0xb36", "arm1136j-s") 1109 .Case("0xb56", "arm1156t2-s") 1110 .Case("0xb76", "arm1176jz-s") 1111 .Case("0xc08", "cortex-a8") 1112 .Case("0xc09", "cortex-a9") 1113 .Case("0xc0f", "cortex-a15") 1114 .Case("0xc20", "cortex-m0") 1115 .Case("0xc23", "cortex-m3") 1116 .Case("0xc24", "cortex-m4") 1117 .Default("generic"); 1118 1119 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 1120 // Look for the CPU part line. 1121 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1122 if (Lines[I].startswith("CPU part")) 1123 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 1124 // values correspond to the "Part number" in the CP15/c0 register. The 1125 // contents are specified in the various processor manuals. 1126 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 1127 .Case("0x06f", "krait") // APQ8064 1128 .Default("generic"); 1129 1130 return "generic"; 1131 } 1132 #elif defined(__linux__) && defined(__s390x__) 1133 StringRef sys::getHostCPUName() { 1134 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 1135 1136 // The "processor 0:" line comes after a fair amount of other information, 1137 // including a cache breakdown, but this should be plenty. 1138 char buffer[2048]; 1139 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 1140 if (CPUInfoSize == -1) 1141 return "generic"; 1142 1143 StringRef Str(buffer, CPUInfoSize); 1144 SmallVector<StringRef, 32> Lines; 1145 Str.split(Lines, "\n"); 1146 1147 // Look for the CPU features. 1148 SmallVector<StringRef, 32> CPUFeatures; 1149 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1150 if (Lines[I].startswith("features")) { 1151 size_t Pos = Lines[I].find(":"); 1152 if (Pos != StringRef::npos) { 1153 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 1154 break; 1155 } 1156 } 1157 1158 // We need to check for the presence of vector support independently of 1159 // the machine type, since we may only use the vector register set when 1160 // supported by the kernel (and hypervisor). 1161 bool HaveVectorSupport = false; 1162 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1163 if (CPUFeatures[I] == "vx") 1164 HaveVectorSupport = true; 1165 } 1166 1167 // Now check the processor machine type. 1168 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 1169 if (Lines[I].startswith("processor ")) { 1170 size_t Pos = Lines[I].find("machine = "); 1171 if (Pos != StringRef::npos) { 1172 Pos += sizeof("machine = ") - 1; 1173 unsigned int Id; 1174 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 1175 if (Id >= 2964 && HaveVectorSupport) 1176 return "z13"; 1177 if (Id >= 2827) 1178 return "zEC12"; 1179 if (Id >= 2817) 1180 return "z196"; 1181 } 1182 } 1183 break; 1184 } 1185 } 1186 1187 return "generic"; 1188 } 1189 #else 1190 StringRef sys::getHostCPUName() { return "generic"; } 1191 #endif 1192 1193 #if defined(__linux__) && defined(__x86_64__) 1194 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1195 // using the number of unique physical/core id pairs. The following 1196 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1197 static int computeHostNumPhysicalCores() { 1198 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1199 // mmapped because it appears to have 0 size. 1200 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1201 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1202 if (std::error_code EC = Text.getError()) { 1203 llvm::errs() << "Can't read " 1204 << "/proc/cpuinfo: " << EC.message() << "\n"; 1205 } 1206 SmallVector<StringRef, 8> strs; 1207 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1208 /*KeepEmpty=*/false); 1209 int CurPhysicalId = -1; 1210 int CurCoreId = -1; 1211 SmallSet<std::pair<int, int>, 32> UniqueItems; 1212 for (auto &Line : strs) { 1213 Line = Line.trim(); 1214 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1215 continue; 1216 std::pair<StringRef, StringRef> Data = Line.split(':'); 1217 auto Name = Data.first.trim(); 1218 auto Val = Data.second.trim(); 1219 if (Name == "physical id") { 1220 assert(CurPhysicalId == -1 && 1221 "Expected a core id before seeing another physical id"); 1222 Val.getAsInteger(10, CurPhysicalId); 1223 } 1224 if (Name == "core id") { 1225 assert(CurCoreId == -1 && 1226 "Expected a physical id before seeing another core id"); 1227 Val.getAsInteger(10, CurCoreId); 1228 } 1229 if (CurPhysicalId != -1 && CurCoreId != -1) { 1230 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1231 CurPhysicalId = -1; 1232 CurCoreId = -1; 1233 } 1234 } 1235 return UniqueItems.size(); 1236 } 1237 #elif defined(__APPLE__) && defined(__x86_64__) 1238 #include <sys/param.h> 1239 #include <sys/sysctl.h> 1240 1241 // Gets the number of *physical cores* on the machine. 1242 static int computeHostNumPhysicalCores() { 1243 uint32_t count; 1244 size_t len = sizeof(count); 1245 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1246 if (count < 1) { 1247 int nm[2]; 1248 nm[0] = CTL_HW; 1249 nm[1] = HW_AVAILCPU; 1250 sysctl(nm, 2, &count, &len, NULL, 0); 1251 if (count < 1) 1252 return -1; 1253 } 1254 return count; 1255 } 1256 #else 1257 // On other systems, return -1 to indicate unknown. 1258 static int computeHostNumPhysicalCores() { return -1; } 1259 #endif 1260 1261 int sys::getHostNumPhysicalCores() { 1262 static int NumCores = computeHostNumPhysicalCores(); 1263 return NumCores; 1264 } 1265 1266 #if defined(__i386__) || defined(_M_IX86) || \ 1267 defined(__x86_64__) || defined(_M_X64) 1268 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1269 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1270 unsigned MaxLevel; 1271 union { 1272 unsigned u[3]; 1273 char c[12]; 1274 } text; 1275 1276 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1277 MaxLevel < 1) 1278 return false; 1279 1280 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1281 1282 Features["cmov"] = (EDX >> 15) & 1; 1283 Features["mmx"] = (EDX >> 23) & 1; 1284 Features["sse"] = (EDX >> 25) & 1; 1285 Features["sse2"] = (EDX >> 26) & 1; 1286 Features["sse3"] = (ECX >> 0) & 1; 1287 Features["ssse3"] = (ECX >> 9) & 1; 1288 Features["sse4.1"] = (ECX >> 19) & 1; 1289 Features["sse4.2"] = (ECX >> 20) & 1; 1290 1291 Features["pclmul"] = (ECX >> 1) & 1; 1292 Features["cx16"] = (ECX >> 13) & 1; 1293 Features["movbe"] = (ECX >> 22) & 1; 1294 Features["popcnt"] = (ECX >> 23) & 1; 1295 Features["aes"] = (ECX >> 25) & 1; 1296 Features["rdrnd"] = (ECX >> 30) & 1; 1297 1298 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1299 // indicates that the AVX registers will be saved and restored on context 1300 // switch, then we have full AVX support. 1301 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1302 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1303 Features["avx"] = HasAVXSave; 1304 Features["fma"] = HasAVXSave && (ECX >> 12) & 1; 1305 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; 1306 1307 // Only enable XSAVE if OS has enabled support for saving YMM state. 1308 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; 1309 1310 // AVX512 requires additional context to be saved by the OS. 1311 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1312 1313 unsigned MaxExtLevel; 1314 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1315 1316 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1317 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1318 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1319 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1320 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1321 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1322 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1323 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1324 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1325 1326 bool HasLeaf7 = 1327 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1328 1329 // AVX2 is only supported if we have the OS save support from AVX. 1330 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); 1331 1332 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1333 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1334 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1335 Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1); 1336 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1337 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1338 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1339 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1340 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1341 Features["smap"] = HasLeaf7 && ((EBX >> 20) & 1); 1342 Features["pcommit"] = HasLeaf7 && ((EBX >> 22) & 1); 1343 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1344 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1345 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1346 1347 // AVX512 is only supported if the OS supports the context save for it. 1348 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1349 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1350 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1351 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1352 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1353 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1354 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1355 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1356 1357 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); 1358 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1359 // Enable protection keys 1360 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1361 1362 bool HasLeafD = MaxLevel >= 0xd && 1363 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1364 1365 // Only enable XSAVE if OS has enabled support for saving YMM state. 1366 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); 1367 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); 1368 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); 1369 1370 return true; 1371 } 1372 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1373 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1374 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line 1375 // in all cases. 1376 char buffer[1024]; 1377 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 1378 if (CPUInfoSize == -1) 1379 return false; 1380 1381 StringRef Str(buffer, CPUInfoSize); 1382 1383 SmallVector<StringRef, 32> Lines; 1384 Str.split(Lines, "\n"); 1385 1386 SmallVector<StringRef, 32> CPUFeatures; 1387 1388 // Look for the CPU features. 1389 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1390 if (Lines[I].startswith("Features")) { 1391 Lines[I].split(CPUFeatures, ' '); 1392 break; 1393 } 1394 1395 #if defined(__aarch64__) 1396 // Keep track of which crypto features we have seen 1397 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1398 uint32_t crypto = 0; 1399 #endif 1400 1401 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1402 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1403 #if defined(__aarch64__) 1404 .Case("asimd", "neon") 1405 .Case("fp", "fp-armv8") 1406 .Case("crc32", "crc") 1407 #else 1408 .Case("half", "fp16") 1409 .Case("neon", "neon") 1410 .Case("vfpv3", "vfp3") 1411 .Case("vfpv3d16", "d16") 1412 .Case("vfpv4", "vfp4") 1413 .Case("idiva", "hwdiv-arm") 1414 .Case("idivt", "hwdiv") 1415 #endif 1416 .Default(""); 1417 1418 #if defined(__aarch64__) 1419 // We need to check crypto separately since we need all of the crypto 1420 // extensions to enable the subtarget feature 1421 if (CPUFeatures[I] == "aes") 1422 crypto |= CAP_AES; 1423 else if (CPUFeatures[I] == "pmull") 1424 crypto |= CAP_PMULL; 1425 else if (CPUFeatures[I] == "sha1") 1426 crypto |= CAP_SHA1; 1427 else if (CPUFeatures[I] == "sha2") 1428 crypto |= CAP_SHA2; 1429 #endif 1430 1431 if (LLVMFeatureStr != "") 1432 Features[LLVMFeatureStr] = true; 1433 } 1434 1435 #if defined(__aarch64__) 1436 // If we have all crypto bits we can add the feature 1437 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1438 Features["crypto"] = true; 1439 #endif 1440 1441 return true; 1442 } 1443 #else 1444 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1445 #endif 1446 1447 std::string sys::getProcessTriple() { 1448 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE)); 1449 1450 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1451 PT = PT.get64BitArchVariant(); 1452 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1453 PT = PT.get32BitArchVariant(); 1454 1455 return PT.str(); 1456 } 1457
