1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===// 2 // 3 // The Subzero Code Generator 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines properties of lowered x86-64 instructions in the 11 // form of x-macros. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef SUBZERO_SRC_ICEINSTX8664_DEF 16 #define SUBZERO_SRC_ICEINSTX8664_DEF 17 18 #include "IceRegList.h" 19 20 // System V AMD64 ABI: 21 // Scratch GPRs: rax, rcx, rdx, rsi, rdi, r8, r9, r10, r11 22 // Callee-save GPRs: rbx, rbp, r12, r13, r14, r15 23 // Scratch XMMs: xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, 24 // xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 25 // Microsoft x86-64 ABI: 26 // Scratch GPRs: rax, rcx, rdx, r8, r9, r10, r11 27 // Callee-save GPRs: rbx, rbp, rsi, rdi, r12, r13, r14, r15 28 // Scratch XMMs: xmm0, xmm1, xmm2, xmm3, xmm4, xmm5 29 // Callee-save XMMs: xmm6-xmm15 30 // Scratch registers are listed first, followed by preserved registers, so 31 // that the register allocator will favor scratch registers. 32 // Key to table columns: 33 // val: Enum value, when a specific register is needed during lowering. 34 // encode: Encoding in the integrated assembler. 35 // name: Name used for the external assembler. 36 // scratch: Scratch (caller-save) register. 37 // preserved: Preserved (callee-save) register. 38 // stackptr: This register is used as the stack pointer. 39 // frameptr: This register is used as the frame pointer if needed. 40 // sboxres: This register is reserved in sandboxing. 41 // isGPR: This is a GPR (integer-type). 42 // is64: This is a 64-bit GPR. 43 // is32: This is a 32-bit GPR. 44 // is16: This is a 16-bit GPR. 45 // is8: This is an 8-bit GPR. 46 // isXmm: This is an XMM register for FP and vector ops. 47 // is64To8: A 64-bit GPR truncable to 8-bit. 48 // is32To8: A 32-bit GPR truncable to 8-bit. 49 // is16To8: A 16-bit GPR truncable to 8-bit. 50 // isTrunc8Rcvr: An 8-bit GPR that a wider GPR trivially truncates to. 51 // isAhRcvr: An 8-bit GPR that register "ah" can be assigned to. 52 // aliases: List of register aliases, which need not include this register. 53 #define REGX8664_BYTEREG_TABLE2(U, W) \ 54 /* val, encode, name, base, scratch,preserved,stackptr,frameptr,sboxres, \ 55 isGPR,is64,is32,is16,is8, isXmm, \ 56 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \ 57 /* 8-bit registers */ \ 58 X(Reg_al, 0, "al", Reg_rax, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \ 59 REGLIST3(RegX8664, rax, eax, ax)) \ 60 X(Reg_cl, 1, "cl", Reg_rcx, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \ 61 REGLIST3(RegX8664, rcx, ecx, cx)) \ 62 X(Reg_dl, 2, "dl", Reg_rdx, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \ 63 REGLIST3(RegX8664, rdx, edx, dx)) \ 64 X(Reg_r8l, 8, "r8b", Reg_r8, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 65 REGLIST3(RegX8664, r8, r8d, r8w)) \ 66 X(Reg_r9l, 9, "r9b", Reg_r9, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 67 REGLIST3(RegX8664, r9, r9d, r9w)) \ 68 X(Reg_r10l, 10, "r10b", Reg_r10, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 69 REGLIST3(RegX8664, r10, r10d, r10w)) \ 70 X(Reg_r11l, 11, "r11b", Reg_r11, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 71 REGLIST3(RegX8664, r11, r11d, r11w)) \ 72 X(Reg_sil, 6, "sil", Reg_rsi, U,W,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 73 REGLIST3(RegX8664, rsi, esi, si)) \ 74 X(Reg_dil, 7, "dil", Reg_rdi, U,W,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 75 REGLIST3(RegX8664, rdi, edi, di)) \ 76 X(Reg_bl, 3, "bl", Reg_rbx, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \ 77 REGLIST3(RegX8664, rbx, ebx, bx)) \ 78 X(Reg_spl, 4, "spl", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \ 79 REGLIST3(RegX8664, rsp, esp, sp)) \ 80 X(Reg_bpl, 5, "bpl", Reg_rbp, 0,1,0,1,1, 1,0,0,0,1, 0, 0,0,0,1,0, \ 81 REGLIST3(RegX8664, rbp, ebp, bp)) \ 82 X(Reg_r12l, 12, "r12b", Reg_r12, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 83 REGLIST3(RegX8664, r12, r12d, r12w)) \ 84 X(Reg_r13l, 13, "r13b", Reg_r13, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 85 REGLIST3(RegX8664, r13, r13d, r13w)) \ 86 X(Reg_r14l, 14, "r14b", Reg_r14, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 87 REGLIST3(RegX8664, r14, r14d, r14w)) \ 88 X(Reg_r15l, 15, "r15b", Reg_r15, 0,1,0,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \ 89 REGLIST3(RegX8664, r15, r15d, r15w)) \ 90 /* High 8-bit registers. None are allowed for register allocation. */ \ 91 X(Reg_ah, 4, "ah", Reg_rax, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \ 92 REGLIST3(RegX8664, rax, eax, ax)) \ 93 X(Reg_ch, 5, "ch", Reg_rcx, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \ 94 REGLIST3(RegX8664, rcx, ecx, cx)) \ 95 X(Reg_dh, 6, "dh", Reg_rdx, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \ 96 REGLIST3(RegX8664, rdx, edx, dx)) \ 97 X(Reg_bh, 7, "bh", Reg_rbx, 0,1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \ 98 REGLIST3(RegX8664, rbx, ebx, bx)) \ 99 /* End of 8-bit register set */ 100 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, 101 // sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, 102 // is16To8, isTrunc8Rcvr, isAhRcvr, aliases) 103 104 #define REGX8664_GPR_TABLE2(U, W) \ 105 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \ 106 isGPR,is64,is32,is16,is8, isXmm, \ 107 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \ 108 /* 64-bit registers */ \ 109 X(Reg_rax, 0, "rax", Reg_rax, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 110 REGLIST4(RegX8664, eax, ax, al, ah)) \ 111 X(Reg_rcx, 1, "rcx", Reg_rcx, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 112 REGLIST4(RegX8664, ecx, cx, cl, ch)) \ 113 X(Reg_rdx, 2, "rdx", Reg_rdx, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 114 REGLIST4(RegX8664, edx, dx, dl, dh)) \ 115 X(Reg_r8, 8, "r8", Reg_r8, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 116 REGLIST3(RegX8664, r8d, r8w, r8l)) \ 117 X(Reg_r9, 9, "r9", Reg_r9, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 118 REGLIST3(RegX8664, r9d, r9w, r9l)) \ 119 X(Reg_r10, 10, "r10", Reg_r10, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 120 REGLIST3(RegX8664, r10d, r10w, r10l)) \ 121 X(Reg_r11, 11, "r11", Reg_r11, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 122 REGLIST3(RegX8664, r11d, r11w, r11l)) \ 123 X(Reg_rsi, 6, "rsi", Reg_rsi, U,W,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 124 REGLIST3(RegX8664, esi, si, sil)) \ 125 X(Reg_rdi, 7, "rdi", Reg_rdi, U,W,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 126 REGLIST3(RegX8664, edi, di, dil)) \ 127 X(Reg_rbx, 3, "rbx", Reg_rbx, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 128 REGLIST4(RegX8664, ebx, bx, bl, bh)) \ 129 X(Reg_rsp, 4, "rsp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 1,0,0,0,0, \ 130 REGLIST3(RegX8664, esp, sp, spl)) \ 131 X(Reg_rbp, 5, "rbp", Reg_rbp, 0,1,0,1,1, 1,1,0,0,0, 0, 1,0,0,0,0, \ 132 REGLIST3(RegX8664, ebp, bp, bpl)) \ 133 X(Reg_r12, 12, "r12", Reg_r12, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 134 REGLIST3(RegX8664, r12d, r12w, r12l)) \ 135 X(Reg_r13, 13, "r13", Reg_r13, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 136 REGLIST3(RegX8664, r13d, r13w, r13l)) \ 137 X(Reg_r14, 14, "r14", Reg_r14, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 138 REGLIST3(RegX8664, r14d, r14w, r14l)) \ 139 X(Reg_r15, 15, "r15", Reg_r15, 0,1,0,0,1, 1,1,0,0,0, 0, 1,0,0,0,0, \ 140 REGLIST3(RegX8664, r15d, r15w, r15l)) \ 141 /* 32-bit registers */ \ 142 X(Reg_eax, 0, "eax", Reg_rax, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 143 REGLIST4(RegX8664, rax, ax, al, ah)) \ 144 X(Reg_ecx, 1, "ecx", Reg_rcx, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 145 REGLIST4(RegX8664, rcx, cx, cl, ch)) \ 146 X(Reg_edx, 2, "edx", Reg_rdx, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 147 REGLIST4(RegX8664, rdx, dx, dl, dh)) \ 148 X(Reg_r8d, 8, "r8d", Reg_r8, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 149 REGLIST3(RegX8664, r8, r8w, r8l)) \ 150 X(Reg_r9d, 9, "r9d", Reg_r9, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 151 REGLIST3(RegX8664, r9, r9w, r9l)) \ 152 X(Reg_r10d, 10, "r10d", Reg_r10, 1,0,0,1,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 153 REGLIST3(RegX8664, r10, r10w, r10l)) \ 154 X(Reg_r11d, 11, "r11d", Reg_r11, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 155 REGLIST3(RegX8664, r11, r11w, r11l)) \ 156 X(Reg_esi, 6, "esi", Reg_rsi, U,W,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 157 REGLIST3(RegX8664, rsi, si, sil)) \ 158 X(Reg_edi, 7, "edi", Reg_rdi, U,W,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 159 REGLIST3(RegX8664, rdi, di, dil)) \ 160 X(Reg_ebx, 3, "ebx", Reg_rbx, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 161 REGLIST4(RegX8664, rbx, bx, bl, bh)) \ 162 X(Reg_esp, 4, "esp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \ 163 REGLIST3(RegX8664, rsp, sp, spl)) \ 164 X(Reg_ebp, 5, "ebp", Reg_rbp, 0,1,0,1,1, 1,0,1,0,0, 0, 0,1,0,0,0, \ 165 REGLIST3(RegX8664, rbp, bp, bpl)) \ 166 X(Reg_r12d, 12, "r12d", Reg_r12, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 167 REGLIST3(RegX8664, r12, r12w, r12l)) \ 168 X(Reg_r13d, 13, "r13d", Reg_r13, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 169 REGLIST3(RegX8664, r13, r13w, r13l)) \ 170 X(Reg_r14d, 14, "r14d", Reg_r14, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 171 REGLIST3(RegX8664, r14, r14w, r14l)) \ 172 X(Reg_r15d, 15, "r15d", Reg_r15, 0,1,0,0,1, 1,0,1,0,0, 0, 0,1,0,0,0, \ 173 REGLIST3(RegX8664, r15, r15w, r15l)) \ 174 /* 16-bit registers */ \ 175 X(Reg_ax, 0, "ax", Reg_rax, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 176 REGLIST4(RegX8664, rax, eax, al, ah)) \ 177 X(Reg_cx, 1, "cx", Reg_rcx, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 178 REGLIST4(RegX8664, rcx, ecx, cl, ch)) \ 179 X(Reg_dx, 2, "dx", Reg_rdx, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 180 REGLIST4(RegX8664, rdx, edx, dl, dh)) \ 181 X(Reg_r8w, 8, "r8w", Reg_r8, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 182 REGLIST3(RegX8664, r8, r8d, r8l)) \ 183 X(Reg_r9w, 9, "r9w", Reg_r9, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 184 REGLIST3(RegX8664, r9, r9d, r9l)) \ 185 X(Reg_r10w, 10, "r10w", Reg_r10, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 186 REGLIST3(RegX8664, r10, r10d, r10l)) \ 187 X(Reg_r11w, 11, "r11w", Reg_r11, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 188 REGLIST3(RegX8664, r11, r11d, r11l)) \ 189 X(Reg_si, 6, "si", Reg_rsi, U,W,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 190 REGLIST3(RegX8664, rsi, esi, sil)) \ 191 X(Reg_di, 7, "di", Reg_rdi, U,W,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 192 REGLIST3(RegX8664, rdi, edi, dil)) \ 193 X(Reg_bx, 3, "bx", Reg_rbx, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 194 REGLIST4(RegX8664, rbx, ebx, bl, bh)) \ 195 X(Reg_sp, 4, "sp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \ 196 REGLIST3(RegX8664, rsp, esp, spl)) \ 197 X(Reg_bp, 5, "bp", Reg_rbp, 0,1,0,1,1, 1,0,0,1,0, 0, 0,0,1,0,0, \ 198 REGLIST3(RegX8664, rbp, ebp, bpl)) \ 199 X(Reg_r12w, 12, "r12w", Reg_r12, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 200 REGLIST3(RegX8664, r12, r12d, r12l)) \ 201 X(Reg_r13w, 13, "r13w", Reg_r13, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 202 REGLIST3(RegX8664, r13, r13d, r13l)) \ 203 X(Reg_r14w, 14, "r14w", Reg_r14, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 204 REGLIST3(RegX8664, r14, r14d, r14l)) \ 205 X(Reg_r15w, 15, "r15w", Reg_r15, 0,1,0,0,1, 1,0,0,1,0, 0, 0,0,1,0,0, \ 206 REGLIST3(RegX8664, r15, r15d, r15l)) \ 207 /* 8-bit registers */ \ 208 REGX8664_BYTEREG_TABLE \ 209 /* End of GPR register set */ 210 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, 211 // sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, 212 // is16To8, isTrunc8Rcvr, isAhRcvr, aliases) 213 214 #if defined(SUBZERO_USE_MICROSOFT_ABI) // Microsoft x86-64 ABI 215 #define REGX8664_BYTEREG_TABLE REGX8664_BYTEREG_TABLE2(0, 1) 216 #define REGX8664_GPR_TABLE REGX8664_GPR_TABLE2(0, 1) 217 #else // System V AMD64 ABI 218 #define REGX8664_BYTEREG_TABLE REGX8664_BYTEREG_TABLE2(1, 0) 219 #define REGX8664_GPR_TABLE REGX8664_GPR_TABLE2(1, 0) 220 #endif 221 222 // Note: It would be more appropriate to list the xmm register aliases as 223 // REGLIST0(), but the corresponding empty initializer gives a syntax error, so 224 // we use REGLIST1() to redundantly assign the register itself as an alias. 225 #define REGX8664_XMM_TABLE \ 226 /* val, encode, name, base, scratch,preserved,stackptr,frameptr,sboxres, \ 227 isGPR,is64,is32,is16,is8, isXmm, \ 228 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \ 229 /* xmm registers */ \ 230 X(Reg_xmm0, 0, "xmm0", Reg_xmm0, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 231 NO_ALIASES()) \ 232 X(Reg_xmm1, 1, "xmm1", Reg_xmm1, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 233 NO_ALIASES()) \ 234 X(Reg_xmm2, 2, "xmm2", Reg_xmm2, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 235 NO_ALIASES()) \ 236 X(Reg_xmm3, 3, "xmm3", Reg_xmm3, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 237 NO_ALIASES()) \ 238 X(Reg_xmm4, 4, "xmm4", Reg_xmm4, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 239 NO_ALIASES()) \ 240 X(Reg_xmm5, 5, "xmm5", Reg_xmm5, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 241 NO_ALIASES()) \ 242 X(Reg_xmm6, 6, "xmm6", Reg_xmm6, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 243 NO_ALIASES()) \ 244 X(Reg_xmm7, 7, "xmm7", Reg_xmm7, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 245 NO_ALIASES()) \ 246 X(Reg_xmm8, 8, "xmm8", Reg_xmm8, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 247 NO_ALIASES()) \ 248 X(Reg_xmm9, 9, "xmm9", Reg_xmm9, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 249 NO_ALIASES()) \ 250 X(Reg_xmm10, 10, "xmm10", Reg_xmm10, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 251 NO_ALIASES()) \ 252 X(Reg_xmm11, 11, "xmm11", Reg_xmm11, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 253 NO_ALIASES()) \ 254 X(Reg_xmm12, 12, "xmm12", Reg_xmm12, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 255 NO_ALIASES()) \ 256 X(Reg_xmm13, 13, "xmm13", Reg_xmm13, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 257 NO_ALIASES()) \ 258 X(Reg_xmm14, 14, "xmm14", Reg_xmm14, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 259 NO_ALIASES()) \ 260 X(Reg_xmm15, 15, "xmm15", Reg_xmm15, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 261 NO_ALIASES()) \ 262 /* End of xmm register set */ 263 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, 264 // sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, 265 // is16To8, isTrunc8Rcvr, isAhRcvr, aliases) 266 267 // We also provide a combined table, so that there is a namespace where 268 // all of the registers are considered and have distinct numberings. 269 // This is in contrast to the above, where the "encode" is based on how 270 // the register numbers will be encoded in binaries and values can overlap. 271 #define REGX8664_TABLE \ 272 REGX8664_GPR_TABLE \ 273 REGX8664_XMM_TABLE 274 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, 275 // sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, 276 // is16To8, isTrunc8Rcvr, isAhRcvr, aliases) 277 278 #define ICEINSTX8664BR_TABLE \ 279 /* val, encode, opposite, dump, emit */ \ 280 X(Br_o, 0, Br_no, "o", "jo") \ 281 X(Br_no, 1, Br_o, "no", "jno") \ 282 X(Br_b, 2, Br_ae, "b", "jb") \ 283 X(Br_ae, 3, Br_b, "ae", "jae") \ 284 X(Br_e, 4, Br_ne, "e", "je") \ 285 X(Br_ne, 5, Br_e, "ne", "jne") \ 286 X(Br_be, 6, Br_a, "be", "jbe") \ 287 X(Br_a, 7, Br_be, "a", "ja") \ 288 X(Br_s, 8, Br_ns, "s", "js") \ 289 X(Br_ns, 9, Br_s, "ns", "jns") \ 290 X(Br_p, 10, Br_np, "p", "jp") \ 291 X(Br_np, 11, Br_p, "np", "jnp") \ 292 X(Br_l, 12, Br_ge, "l", "jl") \ 293 X(Br_ge, 13, Br_l, "ge", "jge") \ 294 X(Br_le, 14, Br_g, "le", "jle") \ 295 X(Br_g, 15, Br_le, "g", "jg") 296 //#define X(val, encode, opp, dump, emit) 297 298 #define ICEINSTX8664CMPPS_TABLE \ 299 /* val, emit */ \ 300 X(Cmpps_eq, "eq") \ 301 X(Cmpps_lt, "lt") \ 302 X(Cmpps_le, "le") \ 303 X(Cmpps_unord, "unord") \ 304 X(Cmpps_neq, "neq") \ 305 X(Cmpps_nlt, "nlt") \ 306 X(Cmpps_nle, "nle") \ 307 X(Cmpps_ord, "ord") 308 //#define X(val, emit) 309 310 #define ICETYPEX8664_TABLE \ 311 /* tag, elty, cvt, sdss, pdps, spsd, int_, unpack, pack, width, fld */ \ 312 X(void, void, "?", "", "", "", "", "", "", "", "") \ 313 X(i1, void, "si", "", "", "", "", "", "", "b", "") \ 314 X(i8, void, "si", "", "", "", "", "", "", "b", "") \ 315 X(i16, void, "si", "", "", "", "", "", "", "w", "") \ 316 X(i32, void, "si", "", "", "", "", "", "", "l", "") \ 317 X(i64, void, "si", "", "", "", "", "", "", "q", "") \ 318 X(f32, void, "ss", "ss", "ps", "ss", "d", "", "", "", "s") \ 319 X(f64, void, "sd", "sd", "pd", "sd", "q", "", "", "", "l") \ 320 X(v4i1, i32, "?", "", "", "", "d", "dq", "", "", "") \ 321 X(v8i1, i16, "?", "", "", "", "w", "wd", "", "", "") \ 322 X(v16i1, i8, "?", "", "", "", "b", "bw", "", "", "") \ 323 X(v16i8, i8, "?", "", "", "", "b", "bw", "", "", "") \ 324 X(v8i16, i16, "?", "", "", "", "w", "wd", "wb", "", "") \ 325 X(v4i32, i32, "dq", "", "", "", "d", "dq", "dw", "", "") \ 326 X(v4f32, f32, "ps", "", "ps", "ps", "d", "dq", "", "", "") 327 //#define X(tag, elty, cvt, sdss, pdps, spsd, int_, unpack, pack, width, fld) 328 329 #endif // SUBZERO_SRC_ICEINSTX8664_DEF 330
