Home | History | Annotate | Download | only in src 
      1 // This file was auto generated by the gen_arm32_reg_tables.py script.
      2 // Do not modify it: modify the script instead.
      3 
      4 #ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF
      5 #define SUBZERO_SRC_ICEREGISTERSARM32_DEF
      6 
      7 //define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
      8 #define REGARM32_GPR_TABLE \
      9   X(Reg_r0, 0, "r0", 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r0, r0r1)) \
     10   X(Reg_r1, 1, "r1", 2, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r1, r0r1)) \
     11   X(Reg_r2, 2, "r2", 3, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r2, r2r3)) \
     12   X(Reg_r3, 3, "r3", 4, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r3, r2r3)) \
     13   X(Reg_r4, 4, "r4", 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r4, r4r5)) \
     14   X(Reg_r5, 5, "r5", 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r5, r4r5)) \
     15   X(Reg_r6, 6, "r6", 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r6, r6r7)) \
     16   X(Reg_r7, 7, "r7", 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r7, r6r7)) \
     17   X(Reg_r8, 8, "r8", 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r8, r8r9)) \
     18   X(Reg_r9, 9, "r9", 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST2(RegARM32, r9, r8r9)) \
     19   X(Reg_r10, 10, "r10", 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r10, r10fp)) \
     20   X(Reg_fp, 11, "fp", 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, fp, r10fp)) \
     21   X(Reg_ip, 12, "ip", 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, ip)) \
     22   X(Reg_sp, 13, "sp", 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, sp)) \
     23   X(Reg_lr, 14, "lr", 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, lr)) \
     24   X(Reg_pc, 15, "pc", 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, pc))
     25 
     26 //define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
     27 #define REGARM32_I64PAIR_TABLE \
     28   X(Reg_r0r1, 0, "r0, r1", 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r0r1, r0, r1)) \
     29   X(Reg_r2r3, 2, "r2, r3", 2, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r2r3, r2, r3)) \
     30   X(Reg_r4r5, 4, "r4, r5", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r4r5, r4, r5)) \
     31   X(Reg_r6r7, 6, "r6, r7", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r6r7, r6, r7)) \
     32   X(Reg_r8r9, 8, "r8, r9", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r8r9, r8, r9)) \
     33   X(Reg_r10fp, 10, "r10, fp", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r10fp, r10, fp))
     34 
     35 //define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
     36 #define REGARM32_FP32_TABLE \
     37   X(Reg_s0, 0, "s0", 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s0, d0, q0)) \
     38   X(Reg_s1, 1, "s1", 2, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s1, d0, q0)) \
     39   X(Reg_s2, 2, "s2", 3, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s2, d1, q0)) \
     40   X(Reg_s3, 3, "s3", 4, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s3, d1, q0)) \
     41   X(Reg_s4, 4, "s4", 5, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s4, d2, q1)) \
     42   X(Reg_s5, 5, "s5", 6, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s5, d2, q1)) \
     43   X(Reg_s6, 6, "s6", 7, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s6, d3, q1)) \
     44   X(Reg_s7, 7, "s7", 8, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s7, d3, q1)) \
     45   X(Reg_s8, 8, "s8", 9, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s8, d4, q2)) \
     46   X(Reg_s9, 9, "s9", 10, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s9, d4, q2)) \
     47   X(Reg_s10, 10, "s10", 11, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s10, d5, q2)) \
     48   X(Reg_s11, 11, "s11", 12, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s11, d5, q2)) \
     49   X(Reg_s12, 12, "s12", 13, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s12, d6, q3)) \
     50   X(Reg_s13, 13, "s13", 14, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s13, d6, q3)) \
     51   X(Reg_s14, 14, "s14", 15, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s14, d7, q3)) \
     52   X(Reg_s15, 15, "s15", 16, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s15, d7, q3)) \
     53   X(Reg_s16, 16, "s16", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s16, d8, q4)) \
     54   X(Reg_s17, 17, "s17", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s17, d8, q4)) \
     55   X(Reg_s18, 18, "s18", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s18, d9, q4)) \
     56   X(Reg_s19, 19, "s19", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s19, d9, q4)) \
     57   X(Reg_s20, 20, "s20", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s20, d10, q5)) \
     58   X(Reg_s21, 21, "s21", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s21, d10, q5)) \
     59   X(Reg_s22, 22, "s22", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s22, d11, q5)) \
     60   X(Reg_s23, 23, "s23", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s23, d11, q5)) \
     61   X(Reg_s24, 24, "s24", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s24, d12, q6)) \
     62   X(Reg_s25, 25, "s25", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s25, d12, q6)) \
     63   X(Reg_s26, 26, "s26", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s26, d13, q6)) \
     64   X(Reg_s27, 27, "s27", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s27, d13, q6)) \
     65   X(Reg_s28, 28, "s28", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s28, d14, q7)) \
     66   X(Reg_s29, 29, "s29", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s29, d14, q7)) \
     67   X(Reg_s30, 30, "s30", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s30, d15, q7)) \
     68   X(Reg_s31, 31, "s31", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s31, d15, q7))
     69 
     70 //define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
     71 #define REGARM32_FP64_TABLE \
     72   X(Reg_d0, 0, "d0", 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d0, q0, s0, s1)) \
     73   X(Reg_d1, 1, "d1", 2, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d1, q0, s2, s3)) \
     74   X(Reg_d2, 2, "d2", 3, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d2, q1, s4, s5)) \
     75   X(Reg_d3, 3, "d3", 4, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d3, q1, s6, s7)) \
     76   X(Reg_d4, 4, "d4", 5, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d4, q2, s8, s9)) \
     77   X(Reg_d5, 5, "d5", 6, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d5, q2, s10, s11)) \
     78   X(Reg_d6, 6, "d6", 7, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d6, q3, s12, s13)) \
     79   X(Reg_d7, 7, "d7", 8, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d7, q3, s14, s15)) \
     80   X(Reg_d8, 8, "d8", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d8, q4, s16, s17)) \
     81   X(Reg_d9, 9, "d9", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d9, q4, s18, s19)) \
     82   X(Reg_d10, 10, "d10", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d10, q5, s20, s21)) \
     83   X(Reg_d11, 11, "d11", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d11, q5, s22, s23)) \
     84   X(Reg_d12, 12, "d12", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d12, q6, s24, s25)) \
     85   X(Reg_d13, 13, "d13", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d13, q6, s26, s27)) \
     86   X(Reg_d14, 14, "d14", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d14, q7, s28, s29)) \
     87   X(Reg_d15, 15, "d15", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d15, q7, s30, s31)) \
     88   X(Reg_d16, 16, "d16", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d16, q8)) \
     89   X(Reg_d17, 17, "d17", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d17, q8)) \
     90   X(Reg_d18, 18, "d18", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d18, q9)) \
     91   X(Reg_d19, 19, "d19", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d19, q9)) \
     92   X(Reg_d20, 20, "d20", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d20, q10)) \
     93   X(Reg_d21, 21, "d21", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d21, q10)) \
     94   X(Reg_d22, 22, "d22", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d22, q11)) \
     95   X(Reg_d23, 23, "d23", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d23, q11)) \
     96   X(Reg_d24, 24, "d24", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d24, q12)) \
     97   X(Reg_d25, 25, "d25", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d25, q12)) \
     98   X(Reg_d26, 26, "d26", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d26, q13)) \
     99   X(Reg_d27, 27, "d27", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d27, q13)) \
    100   X(Reg_d28, 28, "d28", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d28, q14)) \
    101   X(Reg_d29, 29, "d29", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d29, q14)) \
    102   X(Reg_d30, 30, "d30", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d30, q15)) \
    103   X(Reg_d31, 31, "d31", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d31, q15))
    104 
    105 //define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
    106 #define REGARM32_VEC128_TABLE \
    107   X(Reg_q0, 0, "q0", 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q0, d0, d1, s0, s1, s2, s3)) \
    108   X(Reg_q1, 1, "q1", 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q1, d2, d3, s4, s5, s6, s7)) \
    109   X(Reg_q2, 2, "q2", 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q2, d4, d5, s8, s9, s10, s11)) \
    110   X(Reg_q3, 3, "q3", 4, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q3, d6, d7, s12, s13, s14, s15)) \
    111   X(Reg_q4, 4, "q4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q4, d8, d9, s16, s17, s18, s19)) \
    112   X(Reg_q5, 5, "q5", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q5, d10, d11, s20, s21, s22, s23)) \
    113   X(Reg_q6, 6, "q6", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q6, d12, d13, s24, s25, s26, s27)) \
    114   X(Reg_q7, 7, "q7", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q7, d14, d15, s28, s29, s30, s31)) \
    115   X(Reg_q8, 8, "q8", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q8, d16, d17)) \
    116   X(Reg_q9, 9, "q9", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q9, d18, d19)) \
    117   X(Reg_q10, 10, "q10", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q10, d20, d21)) \
    118   X(Reg_q11, 11, "q11", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q11, d22, d23)) \
    119   X(Reg_q12, 12, "q12", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q12, d24, d25)) \
    120   X(Reg_q13, 13, "q13", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q13, d26, d27)) \
    121   X(Reg_q14, 14, "q14", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q14, d28, d29)) \
    122   X(Reg_q15, 15, "q15", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q15, d30, d31))
    123 
    124 #endif // SUBZERO_SRC_ICEREGISTERSARM32_DEF
    125