1 ; This tests a simple loop that sums the elements of an input array. 2 ; The O2 check patterns represent the best code currently achieved. 3 4 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ 5 ; RUN: | FileCheck %s 6 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \ 7 ; RUN: | FileCheck --check-prefix=OPTM1 %s 8 9 define internal i32 @simple_loop(i32 %a, i32 %n) { 10 entry: 11 %cmp4 = icmp sgt i32 %n, 0 12 br i1 %cmp4, label %for.body, label %for.end 13 14 for.body: 15 %i.06 = phi i32 [ %inc, %for.body ], [ 0, %entry ] 16 %sum.05 = phi i32 [ %add, %for.body ], [ 0, %entry ] 17 %gep_array = mul i32 %i.06, 4 18 %gep = add i32 %a, %gep_array 19 %__9 = inttoptr i32 %gep to i32* 20 %v0 = load i32, i32* %__9, align 1 21 %add = add i32 %v0, %sum.05 22 %inc = add i32 %i.06, 1 23 %cmp = icmp slt i32 %inc, %n 24 br i1 %cmp, label %for.body, label %for.end 25 26 for.end: 27 %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ] 28 ret i32 %sum.0.lcssa 29 } 30 31 ; CHECK-LABEL: simple_loop 32 ; CHECK: mov ecx,DWORD PTR [esp{{.*}}+0x{{[0-9a-f]+}}] 33 ; CHECK: cmp ecx,0x0 34 ; CHECK-NEXT: j{{le|g}} {{[0-9]}} 35 36 ; Check for the combination of address mode inference, register 37 ; allocation, and load/arithmetic fusing. 38 ; CHECK: [[L:[0-9a-f]+]]{{.*}} add e{{..}},DWORD PTR [e{{..}}+[[IREG:e..]]*4] 39 ; Check for incrementing of the register-allocated induction variable. 40 ; CHECK-NEXT: add [[IREG]],0x1 41 ; Check for comparing the induction variable against the loop size. 42 ; CHECK-NEXT: cmp [[IREG]], 43 ; CHECK-NEXT: jl [[L]] 44 ; 45 ; There's nothing remarkable under Om1 to test for, since Om1 generates 46 ; such atrocious code (by design). 47 ; OPTM1-LABEL: simple_loop 48 ; OPTM1: cmp {{.*}},0x0 49 ; OPTM1: setl 50 ; OPTM1: ret 51
